1/* 2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <common/debug.h> 11#include <cortex_a65.h> 12#include <cpu_macros.S> 13#include <dsu_macros.S> 14#include <plat_macros.S> 15 16/* Hardware handled coherency */ 17#if !HW_ASSISTED_COHERENCY 18#error "Cortex-A65 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS 23#error "Cortex-A65 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26workaround_reset_start cortex_a65, ERRATUM(936184), ERRATA_DSU_936184 27 errata_dsu_936184_wa_impl 28workaround_reset_end cortex_a65, ERRATUM(936184) 29 30check_erratum_custom_start cortex_a65, ERRATUM(936184) 31 check_errata_dsu_936184_impl 32 ret 33check_erratum_custom_end cortex_a65, ERRATUM(936184) 34 35cpu_reset_func_start cortex_a65 36cpu_reset_func_end cortex_a65 37 38func cortex_a65_cpu_pwr_dwn 39 mrs x0, CORTEX_A65_CPUPWRCTLR_EL1 40 orr x0, x0, #CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 41 msr CORTEX_A65_CPUPWRCTLR_EL1, x0 42 isb 43 ret 44endfunc cortex_a65_cpu_pwr_dwn 45 46.section .rodata.cortex_a65_regs, "aS" 47cortex_a65_regs: /* The ascii list of register names to be reported */ 48 .asciz "cpuectlr_el1", "" 49 50func cortex_a65_cpu_reg_dump 51 adr x6, cortex_a65_regs 52 mrs x8, CORTEX_A65_ECTLR_EL1 53 ret 54endfunc cortex_a65_cpu_reg_dump 55 56declare_cpu_ops cortex_a65, CORTEX_A65_MIDR, \ 57 cortex_a65_reset_func, \ 58 cortex_a65_cpu_pwr_dwn 59