1/* 2 * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a55.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A55 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20 .globl cortex_a55_reset_func 21 .globl cortex_a55_core_pwr_dwn 22 23workaround_reset_start cortex_a55, ERRATUM(798953), ERRATA_DSU_798953 24 errata_dsu_798953_wa_impl 25workaround_reset_end cortex_a55, ERRATUM(798953) 26 27check_erratum_custom_start cortex_a55, ERRATUM(798953) 28 check_errata_dsu_798953_impl 29 ret 30check_erratum_custom_end cortex_a55, ERRATUM(798953) 31 32workaround_reset_start cortex_a55, ERRATUM(936184), ERRATA_DSU_936184 33 errata_dsu_936184_wa_impl 34workaround_reset_end cortex_a55, ERRATUM(936184) 35 36check_erratum_custom_start cortex_a55, ERRATUM(936184) 37 check_errata_dsu_936184_impl 38 ret 39check_erratum_custom_end cortex_a55, ERRATUM(936184) 40 41workaround_reset_start cortex_a55, ERRATUM(768277), ERRATA_A55_768277 42 sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE 43workaround_reset_end cortex_a55, ERRATUM(768277) 44 45check_erratum_ls cortex_a55, ERRATUM(768277), CPU_REV(0, 0) 46 47workaround_reset_start cortex_a55, ERRATUM(778703), ERRATA_A55_778703 48 sysreg_bit_set CORTEX_A55_CPUECTLR_EL1, CORTEX_A55_CPUECTLR_EL1_L1WSCTL 49 sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING 50workaround_reset_end cortex_a55, ERRATUM(778703) 51 52check_erratum_custom_start cortex_a55, ERRATUM(778703) 53 mov x16, x30 54 mov x1, #0x00 55 bl cpu_rev_var_ls 56 /* 57 * Check that no private L2 cache is configured 58 */ 59 mrs x1, CORTEX_A55_CLIDR_EL1 60 and x1, x1, CORTEX_A55_CLIDR_EL1_CTYPE3 61 cmp x1, #0 62 mov x2, #ERRATA_NOT_APPLIES 63 csel x0, x0, x2, eq 64 ret x16 65check_erratum_custom_end cortex_a55, ERRATUM(778703) 66 67workaround_reset_start cortex_a55, ERRATUM(798797), ERRATA_A55_798797 68 sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS 69workaround_reset_end cortex_a55, ERRATUM(798797) 70 71check_erratum_ls cortex_a55, ERRATUM(798797), CPU_REV(0, 0) 72 73workaround_reset_start cortex_a55, ERRATUM(846532), ERRATA_A55_846532 74 sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE 75workaround_reset_end cortex_a55, ERRATUM(846532) 76 77check_erratum_ls cortex_a55, ERRATUM(846532), CPU_REV(0, 1) 78 79workaround_reset_start cortex_a55, ERRATUM(903758), ERRATA_A55_903758 80 sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS 81workaround_reset_end cortex_a55, ERRATUM(903758) 82 83check_erratum_ls cortex_a55, ERRATUM(903758), CPU_REV(0, 1) 84 85workaround_reset_start cortex_a55, ERRATUM(1221012), ERRATA_A55_1221012 86 mov x0, #0x0020 87 movk x0, #0x0850, lsl #16 88 msr CPUPOR_EL3, x0 89 mov x0, #0x0000 90 movk x0, #0x1FF0, lsl #16 91 movk x0, #0x2, lsl #32 92 msr CPUPMR_EL3, x0 93 mov x0, #0x03fd 94 movk x0, #0x0110, lsl #16 95 msr CPUPCR_EL3, x0 96 mov x0, #0x1 97 msr CPUPSELR_EL3, x0 98 mov x0, #0x0040 99 movk x0, #0x08D0, lsl #16 100 msr CPUPOR_EL3, x0 101 mov x0, #0x0040 102 movk x0, #0x1FF0, lsl #16 103 movk x0, #0x2, lsl #32 104 msr CPUPMR_EL3, x0 105 mov x0, #0x03fd 106 movk x0, #0x0110, lsl #16 107 msr CPUPCR_EL3, x0 108workaround_reset_end cortex_a55, ERRATUM(1221012) 109 110check_erratum_ls cortex_a55, ERRATUM(1221012), CPU_REV(1, 0) 111 112check_erratum_chosen cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923 113 114/* erratum has no workaround in the cpu. Generic code must take care */ 115add_erratum_entry cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923, NO_APPLY_AT_RESET 116 117cpu_reset_func_start cortex_a55 118cpu_reset_func_end cortex_a55 119 120 /* --------------------------------------------- 121 * HW will do the cache maintenance while powering down 122 * --------------------------------------------- 123 */ 124func cortex_a55_core_pwr_dwn 125 sysreg_bit_set CORTEX_A55_CPUPWRCTLR_EL1, CORTEX_A55_CORE_PWRDN_EN_MASK 126 isb 127 ret 128endfunc cortex_a55_core_pwr_dwn 129 130 /* --------------------------------------------- 131 * This function provides cortex_a55 specific 132 * register information for crash reporting. 133 * It needs to return with x6 pointing to 134 * a list of register names in ascii and 135 * x8 - x15 having values of registers to be 136 * reported. 137 * --------------------------------------------- 138 */ 139.section .rodata.cortex_a55_regs, "aS" 140cortex_a55_regs: /* The ascii list of register names to be reported */ 141 .asciz "cpuectlr_el1", "" 142 143func cortex_a55_cpu_reg_dump 144 adr x6, cortex_a55_regs 145 mrs x8, CORTEX_A55_CPUECTLR_EL1 146 ret 147endfunc cortex_a55_cpu_reg_dump 148 149declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \ 150 cortex_a55_reset_func, \ 151 cortex_a55_core_pwr_dwn 152