1/* 2 * Copyright (c) 2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include "rdaspen-defs.dtsi" 11 12/ { 13 model = "RD-Aspen"; 14 compatible = "arm,rdaspen"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { 20 stdout-path = &soc_serial0; 21 }; 22 23 cpus { 24 #address-cells = <2>; 25 #size-cells = <0>; 26 27 /* Up to 4 clusters with up to 4 CPU cores in each cluster */ 28 CPU_MAP 29 CPUS 30 }; 31 32 L3_CACHE 33 DSU_PMU 34 35 memory@80000000 { 36 device_type = "memory"; 37 38 /* Bank 0: start = 0x0000_0000_8000_0000, size = ~2 GiB (0x7F00_0000) */ 39 /* Bank 1: start = 0x0000_0200_0000_0000, size = 2 GiB (0x8000_0000) */ 40 reg = < 41 0x00000000 0x80000000 0x00000000 0x7F000000 42 0x00000200 0x00000000 0x00000000 0x80000000 43 >; 44 }; 45 46 timer { 47 compatible = "arm,armv8-timer"; 48 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 49 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 50 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 51 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 52 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 53 }; 54 55 soc_clk24mhz: clk24mhz { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <24000000>; 59 clock-output-names = "refclk24mhz"; 60 }; 61 62 soc { 63 compatible = "simple-bus"; 64 #address-cells = <2>; 65 #size-cells = <2>; 66 ranges; 67 68 timer@1a810000 { 69 compatible = "arm,armv7-timer-mem"; 70 reg = <0x0 0x1a810000 0 0x10000>; 71 #address-cells = <1>; 72 #size-cells = <1>; 73 /* Map child space [0x0..0x30000) to parent @ 0x1a810000 */ 74 ranges = <0x0 0x0 0x1a810000 0x00030000>; 75 76 frame@20000 { 77 frame-number = <1>; 78 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 79 reg = <0x20000 0x10000>; 80 }; 81 }; 82 83 gic: interrupt-controller@20000000 { 84 compatible = "arm,gic-v3"; 85 reg = <0x0 0x20000000 0x0 0x10000>, /* GICD */ 86 <0x0 0x200c0000 0x0 0x400000>; /* 16 * GICR */ 87 #interrupt-cells = <3>; 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 interrupt-controller; 92 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 93 94 its1: msi-controller@20040000 { 95 compatible = "arm,gic-v3-its"; 96 reg = <0x0 0x20040000 0x0 0x40000>; 97 msi-controller; 98 #msi-cells = <1>; 99 }; 100 its2: msi-controller@20080000 { 101 compatible = "arm,gic-v3-its"; 102 reg = <0x0 0x20080000 0x0 0x40000>; 103 msi-controller; 104 #msi-cells = <1>; 105 }; 106 }; 107 108 /* UART is fixed as 24MHz, both UARTCLK and PCLK */ 109 soc_serial0: serial@1a400000 { 110 compatible = "arm,pl011", "arm,primecell"; 111 reg = <0x0 0x1a400000 0x0 0x10000>; 112 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 113 clocks = <&soc_clk24mhz>, <&soc_clk24mhz>; 114 clock-names = "uartclk", "apb_pclk"; 115 }; 116 117 watchdog@1a420000 { 118 compatible = "arm,sbsa-gwdt"; 119 reg = <0x0 0x1a420000 0x0 0x10000>, 120 <0x0 0x1a430000 0x0 0x10000>; 121 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 122 }; 123 124 rtc@300d0000 { 125 compatible = "arm,pl031", "arm,primecell"; 126 reg = <0x0 0x300d0000 0x0 0x10000>; 127 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 128 clocks = <&soc_clk24mhz>; 129 clock-names = "apb_pclk"; 130 }; 131 132 virtio-net@30060000 { 133 compatible = "virtio,mmio"; 134 reg = <0x0 0x30060000 0x0 0x10000>; 135 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 136 }; 137 138 /* OS storage */ 139 virtio-block@30020000 { 140 compatible = "virtio,mmio"; 141 reg = <0x0 0x30020000 0x0 0x10000>; 142 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; 143 }; 144 145 /* Distro installation media */ 146 virtio-block@30030000 { 147 compatible = "virtio,mmio"; 148 reg = <0x0 0x30030000 0x0 0x10000>; 149 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 150 }; 151 152 /* SystemReady ACS validation media */ 153 virtio-block@30040000 { 154 compatible = "virtio,mmio"; 155 reg = <0x0 0x30040000 0x0 0x10000>; 156 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 157 }; 158 159 /* User data media */ 160 virtio-block@30050000 { 161 compatible = "virtio,mmio"; 162 reg = <0x0 0x30050000 0x0 0x10000>; 163 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 164 }; 165 166 virtio-rng@30080000 { 167 compatible = "virtio,mmio"; 168 reg = <0x0 0x30080000 0x0 0x10000>; 169 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 170 }; 171 172 }; 173 174 psci { 175 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 176 method = "smc"; 177 cpu_suspend = <0xc4000001>; 178 cpu_off = <0x84000002>; 179 cpu_on = <0xc4000003>; 180 }; 181 182}; 183