1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/bl_common.h> 10 #include <drivers/arm/pl061_gpio.h> 11 #include <lib/gpt_rme/gpt_rme.h> 12 #include <lib/transfer_list.h> 13 #include <plat/common/platform.h> 14 #if ENABLE_RME 15 #ifdef PLAT_qemu 16 #include <qemu_pas_def.h> 17 #elif PLAT_qemu_sbsa 18 #include <qemu_sbsa_pas_def.h> 19 #endif /* PLAT_qemu */ 20 #endif /* ENABLE_RME */ 21 #ifdef PLAT_qemu_sbsa 22 #include <sbsa_platform.h> 23 #endif 24 25 #include "qemu_private.h" 26 27 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 28 BL31_BASE, \ 29 BL31_END - BL31_BASE, \ 30 MT_MEMORY | MT_RW | EL3_PAS) 31 #define MAP_BL31_RO MAP_REGION_FLAT( \ 32 BL_CODE_BASE, \ 33 BL_CODE_END - BL_CODE_BASE, \ 34 MT_CODE | EL3_PAS), \ 35 MAP_REGION_FLAT( \ 36 BL_RO_DATA_BASE, \ 37 BL_RO_DATA_END \ 38 - BL_RO_DATA_BASE, \ 39 MT_RO_DATA | EL3_PAS) 40 41 #if USE_COHERENT_MEM 42 #define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 43 BL_COHERENT_RAM_BASE, \ 44 BL_COHERENT_RAM_END \ 45 - BL_COHERENT_RAM_BASE, \ 46 MT_DEVICE | MT_RW | EL3_PAS) 47 #endif 48 49 #if ENABLE_RME 50 #if (RME_GPT_BITLOCK_BLOCK == 0) 51 #define BITLOCK_BASE UL(0) 52 #define BITLOCK_SIZE UL(0) 53 #else 54 55 /* 56 * Number of bitlock_t entries in the gpt_bitlock array for this platform's 57 * Protected Physical Size. One 8-bit bitlock_t entry covers 58 * 8 * RME_GPT_BITLOCK_BLOCK * 512MB. 59 */ 60 #if (PLAT_QEMU_PPS > (RME_GPT_BITLOCK_BLOCK * SZ_512M * UL(8))) 61 #define BITLOCKS_NUM (PLAT_QEMU_PPS / \ 62 (RME_GPT_BITLOCK_BLOCK * SZ_512M * UL(8))) 63 #else 64 #define BITLOCKS_NUM 1 65 #endif 66 67 static bitlock_t gpt_bitlock[BITLOCKS_NUM]; 68 #define BITLOCK_BASE (uintptr_t)gpt_bitlock 69 #define BITLOCK_SIZE sizeof(gpt_bitlock) 70 #endif /* RME_GPT_BITLOCK_BLOCK */ 71 #endif /* ENABLE_RME */ 72 73 /* 74 * Placeholder variables for copying the arguments that have been passed to 75 * BL3-1 from BL2. 76 */ 77 static entry_point_info_t bl32_image_ep_info; 78 static entry_point_info_t bl33_image_ep_info; 79 #if ENABLE_RME 80 static entry_point_info_t rmm_image_ep_info; 81 #endif 82 static struct transfer_list_header *bl31_tl; 83 84 /******************************************************************************* 85 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 86 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before 87 * they are lost (potentially). This needs to be done before the MMU is 88 * initialized so that the memory layout can be used while creating page 89 * tables. BL2 has flushed this information to memory, so we are guaranteed 90 * to pick up good data. 91 ******************************************************************************/ 92 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 93 u_register_t arg2, u_register_t arg3) 94 { 95 bool is64 = false; 96 uint64_t hval; 97 98 /* Initialize the console to provide early debug support */ 99 qemu_console_init(); 100 101 /* Platform names have to be lowercase. */ 102 #ifdef PLAT_qemu_sbsa 103 sbsa_platform_init(); 104 #endif 105 106 /* 107 * Check params passed from BL2 108 */ 109 bl_params_t *params_from_bl2 = (bl_params_t *)arg0; 110 111 assert(params_from_bl2); 112 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 113 assert(params_from_bl2->h.version >= VERSION_2); 114 115 bl_params_node_t *bl_params = params_from_bl2->head; 116 117 /* 118 * Copy BL33, BL32 and RMM (if present), entry point information. 119 * They are stored in Secure RAM, in BL2's address space. 120 */ 121 while (bl_params) { 122 #ifdef __aarch64__ 123 if (bl_params->image_id == BL31_IMAGE_ID && 124 GET_RW(bl_params->ep_info->spsr) == MODE_RW_64) 125 is64 = true; 126 #endif 127 if (bl_params->image_id == BL32_IMAGE_ID) 128 bl32_image_ep_info = *bl_params->ep_info; 129 130 #if ENABLE_RME 131 if (bl_params->image_id == RMM_IMAGE_ID) 132 rmm_image_ep_info = *bl_params->ep_info; 133 #endif 134 135 if (bl_params->image_id == BL33_IMAGE_ID) 136 bl33_image_ep_info = *bl_params->ep_info; 137 138 bl_params = bl_params->next_params_info; 139 } 140 141 if (!bl33_image_ep_info.pc) 142 panic(); 143 #if ENABLE_RME 144 if (!rmm_image_ep_info.pc) 145 panic(); 146 #endif 147 148 if (!TRANSFER_LIST || 149 !transfer_list_check_header((void *)arg3)) 150 return; 151 152 if (is64) 153 hval = TRANSFER_LIST_HANDOFF_X1_VALUE(REGISTER_CONVENTION_VERSION); 154 else 155 hval = TRANSFER_LIST_HANDOFF_R1_VALUE(REGISTER_CONVENTION_VERSION); 156 157 if (arg1 != hval) 158 return; 159 160 bl31_tl = (void *)arg3; /* saved TL address from BL2 */ 161 } 162 163 #if ENABLE_RME 164 #if PLAT_qemu 165 /* 166 * The GPT library might modify the gpt regions structure to optimize 167 * the layout, so the array cannot be constant. 168 */ 169 static pas_region_t pas_regions[] = { 170 QEMU_PAS_ROOT, 171 QEMU_PAS_SECURE, 172 QEMU_PAS_GPTS, 173 QEMU_PAS_NS0, 174 QEMU_PAS_REALM, 175 QEMU_PAS_NS1, 176 }; 177 178 static inline void bl31_adjust_pas_regions(void) {} 179 #elif PLAT_qemu_sbsa 180 /* 181 * The GPT library might modify the gpt regions structure to optimize 182 * the layout, so the array cannot be constant. 183 */ 184 static pas_region_t pas_regions[] = { 185 QEMU_PAS_ROOT, 186 QEMU_PAS_SECURE, 187 QEMU_PAS_GPTS, 188 QEMU_PAS_REALM, 189 QEMU_PAS_NS0, 190 }; 191 192 static void bl31_adjust_pas_regions(void) 193 { 194 uint64_t base_addr = 0, total_size = 0; 195 struct platform_memory_data data; 196 uint32_t node; 197 198 /* 199 * The amount of memory supported by the SBSA platform is dynamic 200 * and dependent on user input. Since the configuration of the GPT 201 * needs to reflect the system memory, QEMU_PAS_NS0 needs to be set 202 * based on the information found in the device tree. 203 */ 204 205 for (node = 0; node < sbsa_platform_num_memnodes(); node++) { 206 data = sbsa_platform_memory_node(node); 207 208 if (data.nodeid == 0) { 209 base_addr = data.addr_base; 210 } 211 212 total_size += data.addr_size; 213 } 214 215 /* Index '4' correspond to QEMU_PAS_NS0, see pas_regions[] above */ 216 pas_regions[4].base_pa = base_addr; 217 pas_regions[4].size = total_size; 218 } 219 #endif /* PLAT_qemu */ 220 221 static void bl31_plat_gpt_setup(void) 222 { 223 /* 224 * Initialize entire protected space to GPT_GPI_ANY. With each L0 entry 225 * covering 1GB (currently the only supported option), then covering 226 * 256TB of RAM (48-bit PA) would require a 2MB L0 region. At the 227 * moment we use a 8KB table, which covers 1TB of RAM (40-bit PA). 228 */ 229 if (gpt_init_l0_tables(PLAT_QEMU_GPCCR_PPS, PLAT_QEMU_L0_GPT_BASE, 230 PLAT_QEMU_L0_GPT_SIZE) < 0) { 231 ERROR("gpt_init_l0_tables() failed!\n"); 232 panic(); 233 } 234 235 bl31_adjust_pas_regions(); 236 237 /* Carve out defined PAS ranges. */ 238 if (gpt_init_pas_l1_tables(GPCCR_PGS_4K, 239 PLAT_QEMU_L1_GPT_BASE, 240 PLAT_QEMU_L1_GPT_SIZE, 241 pas_regions, 242 (unsigned int)(sizeof(pas_regions) / 243 sizeof(pas_region_t))) < 0) { 244 ERROR("gpt_init_pas_l1_tables() failed!\n"); 245 panic(); 246 } 247 248 INFO("Enabling Granule Protection Checks\n"); 249 if (gpt_enable() < 0) { 250 ERROR("gpt_enable() failed!\n"); 251 panic(); 252 } 253 } 254 #endif 255 256 void bl31_plat_arch_setup(void) 257 { 258 const mmap_region_t bl_regions[] = { 259 MAP_BL31_TOTAL, 260 MAP_BL31_RO, 261 #if USE_COHERENT_MEM 262 MAP_BL_COHERENT_RAM, 263 #endif 264 #if ENABLE_RME 265 MAP_GPT_L0_REGION, 266 MAP_GPT_L1_REGION, 267 MAP_RMM_SHARED_MEM, 268 #endif 269 {0} 270 }; 271 272 setup_page_tables(bl_regions, plat_qemu_get_mmap()); 273 274 enable_mmu_el3(0); 275 276 #if ENABLE_RME 277 /* Initialise and enable granule protection after MMU. */ 278 bl31_plat_gpt_setup(); 279 280 /* 281 * Initialise Granule Protection library and enable GPC for the primary 282 * processor. The tables have already been initialized by a previous BL 283 * stage, so there is no need to provide any PAS here. This function 284 * sets up pointers to those tables. 285 */ 286 if (gpt_runtime_init(BITLOCK_BASE, BITLOCK_SIZE) < 0) { 287 ERROR("gpt_runtime_init() failed!\n"); 288 panic(); 289 } 290 #endif /* ENABLE_RME */ 291 292 } 293 294 static void qemu_gpio_init(void) 295 { 296 #ifdef SECURE_GPIO_BASE 297 pl061_gpio_init(); 298 pl061_gpio_register(SECURE_GPIO_BASE, 0); 299 #endif 300 } 301 302 void bl31_platform_setup(void) 303 { 304 plat_qemu_gic_init(); 305 qemu_gpio_init(); 306 } 307 308 unsigned int plat_get_syscnt_freq2(void) 309 { 310 return read_cntfrq_el0(); 311 } 312 313 /******************************************************************************* 314 * Return a pointer to the 'entry_point_info' structure of the next image 315 * for the security state specified. BL3-3 corresponds to the non-secure 316 * image type while BL3-2 corresponds to the secure image type. A NULL 317 * pointer is returned if the image does not exist. 318 ******************************************************************************/ 319 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 320 { 321 entry_point_info_t *next_image_info; 322 323 assert(sec_state_is_valid(type)); 324 if (type == NON_SECURE) { 325 next_image_info = &bl33_image_ep_info; 326 } 327 #if ENABLE_RME 328 else if (type == REALM) { 329 next_image_info = &rmm_image_ep_info; 330 } 331 #endif 332 else { 333 next_image_info = &bl32_image_ep_info; 334 } 335 336 /* 337 * None of the images on the ARM development platforms can have 0x0 338 * as the entrypoint 339 */ 340 if (next_image_info->pc) 341 return next_image_info; 342 else 343 return NULL; 344 } 345 346 void bl31_plat_runtime_setup(void) 347 { 348 #if TRANSFER_LIST 349 if (bl31_tl) { 350 /* 351 * Relocate the TL from S to NS memory before EL3 exit 352 * to reflect all changes in TL done by BL32 353 */ 354 if (!transfer_list_relocate(bl31_tl, (void *)FW_NS_HANDOFF_BASE, 355 bl31_tl->max_size)) 356 ERROR("Relocate TL to NS memory failed\n"); 357 } 358 #endif 359 360 console_flush(); 361 console_switch_state(CONSOLE_FLAG_RUNTIME); 362 } 363