1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a510.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A510 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25workaround_reset_start cortex_a510, ERRATUM(1922240), ERRATA_A510_1922240 26 /* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */ 27 sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE, \ 28 CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH 29workaround_reset_end cortex_a510, ERRATUM(1922240) 30 31check_erratum_ls cortex_a510, ERRATUM(1922240), CPU_REV(0, 0) 32 33workaround_reset_start cortex_a510, ERRATUM(2041909), ERRATA_A510_2041909 34 /* Apply workaround */ 35 mov x0, xzr 36 msr S3_6_C15_C4_0, x0 37 isb 38 39 mov x0, #0x8500000 40 msr S3_6_C15_C4_2, x0 41 42 mov x0, #0x1F700000 43 movk x0, #0x8, lsl #32 44 msr S3_6_C15_C4_3, x0 45 46 mov x0, #0x3F1 47 movk x0, #0x110, lsl #16 48 msr S3_6_C15_C4_1, x0 49workaround_reset_end cortex_a510, ERRATUM(2041909) 50 51check_erratum_range cortex_a510, ERRATUM(2041909), CPU_REV(0, 2), CPU_REV(0, 2) 52 53workaround_reset_start cortex_a510, ERRATUM(2042739), ERRATA_A510_2042739 54 /* Apply the workaround by disabling ReadPreferUnique. */ 55 sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE, \ 56 CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH 57workaround_reset_end cortex_a510, ERRATUM(2042739) 58 59check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2) 60 61workaround_reset_start cortex_a510, ERRATUM(2080326), ERRATA_A510_2080326 62 /* Apply workaround */ 63 mov x0, #1 64 msr S3_6_C15_C4_0, x0 65 isb 66 67 mov x0, #0x0100 68 movk x0, #0x0E08, lsl #16 69 msr S3_6_C15_C4_2, x0 70 71 mov x0, #0x0300 72 movk x0, #0x0F1F, lsl #16 73 movk x0, #0x0008, lsl #32 74 msr S3_6_C15_C4_3, x0 75 76 mov x0, #0x03F1 77 movk x0, #0x00C0, lsl #16 78 msr S3_6_C15_C4_1, x0 79 80 isb 81workaround_reset_end cortex_a510, ERRATUM(2080326) 82 83check_erratum_range cortex_a510, ERRATUM(2080326), CPU_REV(0, 2), CPU_REV(0, 2) 84 85workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148 86 /* 87 * Force L2 allocation of transient lines by setting 88 * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01. 89 */ 90 mrs x0, CORTEX_A510_CPUECTLR_EL1 91 mov x1, #1 92 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2 93 bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2 94 msr CORTEX_A510_CPUECTLR_EL1, x0 95workaround_reset_end cortex_a510, ERRATUM(2172148) 96 97check_erratum_ls cortex_a510, ERRATUM(2172148), CPU_REV(1, 0) 98 99workaround_reset_start cortex_a510, ERRATUM(2218950), ERRATA_A510_2218950 100 /* Set bit 18 in CPUACTLR_EL1 */ 101 sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \ 102 CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH 103 104 /* Set bit 25 in CMPXACTLR_EL1 */ 105 sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \ 106 CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH 107 108workaround_reset_end cortex_a510, ERRATUM(2218950) 109 110check_erratum_ls cortex_a510, ERRATUM(2218950), CPU_REV(1, 0) 111 112 /* -------------------------------------------------- 113 * This workaround is not a typical errata fix. MPMM 114 * is disabled here, but this conflicts with the BL31 115 * MPMM support. So in addition to simply disabling 116 * the feature, a flag is set in the MPMM library 117 * indicating that it should not be enabled even if 118 * ENABLE_MPMM=1. 119 * -------------------------------------------------- 120 */ 121workaround_reset_start cortex_a510, ERRATUM(2250311), ERRATA_A510_2250311 122 /* Disable MPMM */ 123 mrs x0, CPUMPMMCR_EL3 124 bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */ 125 msr CPUMPMMCR_EL3, x0 126 127#if ENABLE_MPMM && IMAGE_BL31 128 /* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */ 129 bl mpmm_errata_disable 130#endif 131workaround_reset_end cortex_a510, ERRATUM(2250311) 132 133check_erratum_ls cortex_a510, ERRATUM(2250311), CPU_REV(1, 0) 134 135workaround_reset_start cortex_a510, ERRATUM(2288014), ERRATA_A510_2288014 136 /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */ 137 sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE, \ 138 CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH 139workaround_reset_end cortex_a510, ERRATUM(2288014) 140 141check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0) 142 143workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730 144 /* 145 * Set CPUACTLR_EL1[17] to 1'b1, which disables 146 * specific microarchitectural clock gating 147 * behaviour. 148 */ 149 sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_17 150workaround_reset_end cortex_a510, ERRATUM(2347730) 151 152check_erratum_ls cortex_a510, ERRATUM(2347730), CPU_REV(1, 1) 153 154workaround_reset_start cortex_a510, ERRATUM(2371937), ERRATA_A510_2371937 155 /* 156 * Cacheable atomic operations can be forced 157 * to be executed near by setting 158 * IMP_CPUECTLR_EL1.ATOM=0b010. ATOM is found 159 * in [40:38] of CPUECTLR_EL1. 160 */ 161 sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR, \ 162 CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT, CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH 163workaround_reset_end cortex_a510, ERRATUM(2371937) 164 165check_erratum_ls cortex_a510, ERRATUM(2371937), CPU_REV(1, 1) 166 167workaround_reset_start cortex_a510, ERRATUM(2666669), ERRATA_A510_2666669 168 sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_38 169workaround_reset_end cortex_a510, ERRATUM(2666669) 170 171check_erratum_ls cortex_a510, ERRATUM(2666669), CPU_REV(1, 1) 172 173.global erratum_cortex_a510_2684597_wa 174workaround_runtime_start cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597, CORTEX_A510_MIDR 175 /* 176 * Many assemblers do not yet understand the "tsb csync" mnemonic, 177 * so use the equivalent hint instruction. 178 */ 179 hint #18 /* tsb csync */ 180workaround_runtime_end cortex_a510, ERRATUM(2684597) 181 182check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2) 183 184workaround_reset_start cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941 185 errata_dsu_2313941_wa_impl 186workaround_reset_end cortex_a510, ERRATUM(2313941) 187 188check_erratum_custom_start cortex_a510, ERRATUM(2313941) 189 check_errata_dsu_2313941_impl 190 ret 191check_erratum_custom_end cortex_a510, ERRATUM(2313941) 192 193 /* ---------------------------------------------------- 194 * HW will do the cache maintenance while powering down 195 * ---------------------------------------------------- 196 */ 197func cortex_a510_core_pwr_dwn 198 /* --------------------------------------------------- 199 * Enable CPU power down bit in power control register 200 * --------------------------------------------------- 201 */ 202 sysreg_bit_set CORTEX_A510_CPUPWRCTLR_EL1, CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 203 isb 204 ret 205endfunc cortex_a510_core_pwr_dwn 206 207cpu_reset_func_start cortex_a510 208 /* Disable speculative loads */ 209 msr SSBS, xzr 210cpu_reset_func_end cortex_a510 211 212 /* --------------------------------------------- 213 * This function provides Cortex-A510 specific 214 * register information for crash reporting. 215 * It needs to return with x6 pointing to 216 * a list of register names in ascii and 217 * x8 - x15 having values of registers to be 218 * reported. 219 * --------------------------------------------- 220 */ 221.section .rodata.cortex_a510_regs, "aS" 222cortex_a510_regs: /* The ascii list of register names to be reported */ 223 .asciz "cpuectlr_el1", "" 224 225func cortex_a510_cpu_reg_dump 226 adr x6, cortex_a510_regs 227 mrs x8, CORTEX_A510_CPUECTLR_EL1 228 ret 229endfunc cortex_a510_cpu_reg_dump 230 231declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \ 232 cortex_a510_reset_func, \ 233 cortex_a510_core_pwr_dwn 234