1/* 2 * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue neoverse_v3 26 27.global check_erratum_neoverse_v3_3701767 28 29workaround_reset_start neoverse_v3, ERRATUM(2970647), ERRATA_V3_2970647 30 /* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */ 31 ldr x0, =0x1 32 msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */ 33 ldr x0, =0xd5380000 34 msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */ 35 ldr x0, =0xFFFFFF40 36 msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */ 37 ldr x0, =0x000080010033f 38 msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */ 39 isb 40workaround_reset_end neoverse_v3, ERRATUM(2970647) 41 42check_erratum_ls neoverse_v3, ERRATUM(2970647), CPU_REV(0, 0) 43 44add_erratum_entry neoverse_v3, ERRATUM(3701767), ERRATA_V3_3701767 45 46check_erratum_ls neoverse_v3, ERRATUM(3701767), CPU_REV(0, 2) 47 48#if WORKAROUND_CVE_2022_23960 49 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3 50#endif /* WORKAROUND_CVE_2022_23960 */ 51 52workaround_reset_start neoverse_v3, CVE(2022,23960), WORKAROUND_CVE_2022_23960 53#if IMAGE_BL31 54 /* 55 * The Neoverse V3 generic vectors are overridden to apply errata 56 * mitigation on exception entry from lower ELs. 57 */ 58 override_vector_table wa_cve_vbar_neoverse_v3 59 60#endif /* IMAGE_BL31 */ 61workaround_reset_end neoverse_v3, CVE(2022,23960) 62 63check_erratum_chosen neoverse_v3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 64 65/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 66workaround_reset_start neoverse_v3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 67 sysreg_bit_set NEOVERSE_V3_CPUECTLR_EL1, BIT(46) 68workaround_reset_end neoverse_v3, CVE(2024, 5660) 69 70check_erratum_ls neoverse_v3, CVE(2024, 5660), CPU_REV(0, 1) 71 72workaround_reset_start neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 73 /* --------------------------------- 74 * Sets BIT41 of CPUACTLR6_EL1 which 75 * disables L1 Data cache prefetcher 76 * --------------------------------- 77 */ 78 sysreg_bit_set NEOVERSE_V3_CPUACTLR6_EL1, BIT(41) 79workaround_reset_end neoverse_v3, CVE(2024, 7881) 80 81check_erratum_chosen neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 82 83 /* --------------------------------------------- 84 * HW will do the cache maintenance while powering down 85 * --------------------------------------------- 86 */ 87func neoverse_v3_core_pwr_dwn 88 /* --------------------------------------------- 89 * Enable CPU power down bit in power control register 90 * --------------------------------------------- 91 */ 92 sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \ 93 NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 94 95 isb 96 ret 97endfunc neoverse_v3_core_pwr_dwn 98 99cpu_reset_func_start neoverse_v3 100 /* Disable speculative loads */ 101 msr SSBS, xzr 102cpu_reset_func_end neoverse_v3 103 104 /* --------------------------------------------- 105 * This function provides Neoverse V3 specific 106 * register information for crash reporting. 107 * It needs to return with x6 pointing to 108 * a list of register names in ascii and 109 * x8 - x15 having values of registers to be 110 * reported. 111 * --------------------------------------------- 112 */ 113.section .rodata.neoverse_v3_regs, "aS" 114neoverse_v3_regs: /* The ascii list of register names to be reported */ 115 .asciz "cpuectlr_el1", "" 116 117func neoverse_v3_cpu_reg_dump 118 adr x6, neoverse_v3_regs 119 mrs x8, NEOVERSE_V3_CPUECTLR_EL1 120 ret 121endfunc neoverse_v3_cpu_reg_dump 122 123declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \ 124 neoverse_v3_reset_func, \ 125 neoverse_v3_core_pwr_dwn 126 127declare_cpu_ops_wa_4 neoverse_v3, NEOVERSE_V3_MIDR, \ 128 neoverse_v3_reset_func, \ 129 CPU_NO_EXTRA1_FUNC, \ 130 CPU_NO_EXTRA2_FUNC, \ 131 CPU_NO_EXTRA3_FUNC, \ 132 check_erratum_neoverse_v3_7881, \ 133 neoverse_v3_core_pwr_dwn 134