1 /* 2 * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stddef.h> 9 #include <stdint.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <common/bl_common.h> 17 #include <common/build_message.h> 18 #include <common/debug.h> 19 #include <common/runtime_svc.h> 20 #include <context.h> 21 #include <drivers/console.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/pmf/pmf.h> 24 #include <lib/psci/psci.h> 25 #include <lib/runtime_instr.h> 26 #include <lib/utils.h> 27 #include <plat/common/platform.h> 28 #include <platform_sp_min.h> 29 #include <services/std_svc.h> 30 #include <smccc_helpers.h> 31 32 #include "sp_min_private.h" 33 34 #if ENABLE_RUNTIME_INSTRUMENTATION 35 PMF_REGISTER_SERVICE_SMC(rt_instr_svc, PMF_RT_INSTR_SVC_ID, 36 RT_INSTR_TOTAL_IDS, PMF_STORE_ENABLE) 37 #endif 38 39 /* Pointers to per-core cpu contexts */ 40 static void *sp_min_cpu_ctx_ptr[PLATFORM_CORE_COUNT]; 41 42 /* SP_MIN only stores the non secure smc context */ 43 static smc_ctx_t sp_min_smc_context[PLATFORM_CORE_COUNT]; 44 45 /****************************************************************************** 46 * Define the smccc helper library APIs 47 *****************************************************************************/ 48 void *smc_get_ctx(unsigned int security_state) 49 { 50 assert(security_state == NON_SECURE); 51 return &sp_min_smc_context[plat_my_core_pos()]; 52 } 53 54 void smc_set_next_ctx(unsigned int security_state) 55 { 56 assert(security_state == NON_SECURE); 57 /* SP_MIN stores only non secure smc context. Nothing to do here */ 58 } 59 60 void *smc_get_next_ctx(void) 61 { 62 return &sp_min_smc_context[plat_my_core_pos()]; 63 } 64 65 /******************************************************************************* 66 * This function returns a pointer to the most recent 'cpu_context' structure 67 * for the calling CPU that was set as the context for the specified security 68 * state. NULL is returned if no such structure has been specified. 69 ******************************************************************************/ 70 void *cm_get_context(size_t security_state) 71 { 72 assert(security_state == NON_SECURE); 73 return sp_min_cpu_ctx_ptr[plat_my_core_pos()]; 74 } 75 76 /******************************************************************************* 77 * This function sets the pointer to the current 'cpu_context' structure for the 78 * specified security state for the calling CPU 79 ******************************************************************************/ 80 void cm_set_context(void *context, uint32_t security_state) 81 { 82 assert(security_state == NON_SECURE); 83 sp_min_cpu_ctx_ptr[plat_my_core_pos()] = context; 84 } 85 86 /******************************************************************************* 87 * This function returns a pointer to the most recent 'cpu_context' structure 88 * for the CPU identified by `cpu_idx` that was set as the context for the 89 * specified security state. NULL is returned if no such structure has been 90 * specified. 91 ******************************************************************************/ 92 void *cm_get_context_by_index(unsigned int cpu_idx, 93 size_t security_state) 94 { 95 assert(security_state == NON_SECURE); 96 return sp_min_cpu_ctx_ptr[cpu_idx]; 97 } 98 99 /******************************************************************************* 100 * This function sets the pointer to the current 'cpu_context' structure for the 101 * specified security state for the CPU identified by CPU index. 102 ******************************************************************************/ 103 void cm_set_context_by_index(unsigned int cpu_idx, void *context, 104 unsigned int security_state) 105 { 106 assert(security_state == NON_SECURE); 107 sp_min_cpu_ctx_ptr[cpu_idx] = context; 108 } 109 110 static void copy_cpu_ctx_to_smc_stx(const regs_t *cpu_reg_ctx, 111 smc_ctx_t *next_smc_ctx) 112 { 113 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0); 114 next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1); 115 next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2); 116 next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3); 117 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR); 118 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR); 119 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR); 120 } 121 122 /******************************************************************************* 123 * This function invokes the PSCI library interface to initialize the 124 * non secure cpu context and copies the relevant cpu context register values 125 * to smc context. These registers will get programmed during `smc_exit`. 126 ******************************************************************************/ 127 static void sp_min_prepare_next_image_entry(void) 128 { 129 entry_point_info_t *next_image_info; 130 regs_t *gpregs = get_regs_ctx(cm_get_context(NON_SECURE)); 131 u_register_t ns_sctlr; 132 133 /* Program system registers to proceed to non-secure */ 134 next_image_info = sp_min_plat_get_bl33_ep_info(); 135 assert(next_image_info); 136 assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr)); 137 138 INFO("SP_MIN: Preparing exit to normal world\n"); 139 print_entry_point_info(next_image_info); 140 141 psci_prepare_next_non_secure_ctx(next_image_info); 142 smc_set_next_ctx(NON_SECURE); 143 144 /* Copy r0, lr and spsr from cpu context to SMC context */ 145 copy_cpu_ctx_to_smc_stx(gpregs, 146 smc_get_next_ctx()); 147 148 /* Temporarily set the NS bit to access NS SCTLR */ 149 write_scr(read_scr() | SCR_NS_BIT); 150 isb(); 151 ns_sctlr = read_ctx_reg(gpregs, CTX_NS_SCTLR); 152 write_sctlr(ns_sctlr); 153 isb(); 154 155 write_scr(read_scr() & ~SCR_NS_BIT); 156 isb(); 157 } 158 159 /****************************************************************************** 160 * Implement the ARM Standard Service function to get arguments for a 161 * particular service. 162 *****************************************************************************/ 163 uintptr_t get_arm_std_svc_args(unsigned int svc_mask) 164 { 165 /* Setup the arguments for PSCI Library */ 166 DEFINE_STATIC_PSCI_LIB_ARGS_V1(psci_args, sp_min_warm_entrypoint); 167 168 /* PSCI is the only ARM Standard Service implemented */ 169 assert(svc_mask == PSCI_FID_MASK); 170 171 return (uintptr_t)&psci_args; 172 } 173 174 /****************************************************************************** 175 * The SP_MIN setup function. Calls platforms init functions 176 *****************************************************************************/ 177 void sp_min_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, 178 u_register_t arg3) 179 { 180 /* Enable early console if EARLY_CONSOLE flag is enabled */ 181 plat_setup_early_console(); 182 183 /* Perform early platform-specific setup */ 184 sp_min_early_platform_setup2(arg0, arg1, arg2, arg3); 185 sp_min_plat_arch_setup(); 186 } 187 188 /****************************************************************************** 189 * The SP_MIN main function. Do the platform and PSCI Library setup. Also 190 * initialize the runtime service framework. 191 *****************************************************************************/ 192 void sp_min_main(void) 193 { 194 NOTICE("SP_MIN: %s\n", build_version_string); 195 NOTICE("SP_MIN: %s\n", build_message); 196 197 /* Perform the SP_MIN platform setup */ 198 sp_min_platform_setup(); 199 200 /* Initialize the runtime services e.g. psci */ 201 INFO("SP_MIN: Initializing runtime services\n"); 202 runtime_svc_init(); 203 204 /* 205 * We are ready to enter the next EL. Prepare entry into the image 206 * corresponding to the desired security state after the next ERET. 207 */ 208 sp_min_prepare_next_image_entry(); 209 210 /* 211 * Perform any platform specific runtime setup prior to cold boot exit 212 * from SP_MIN. 213 */ 214 sp_min_plat_runtime_setup(); 215 216 console_flush(); 217 console_switch_state(CONSOLE_FLAG_RUNTIME); 218 } 219 220 /****************************************************************************** 221 * This function is invoked during warm boot. Invoke the PSCI library 222 * warm boot entry point which takes care of Architectural and platform setup/ 223 * restore. Copy the relevant cpu_context register values to smc context which 224 * will get programmed during `smc_exit`. 225 *****************************************************************************/ 226 void sp_min_warm_boot(void) 227 { 228 smc_ctx_t *next_smc_ctx; 229 regs_t *gpregs = get_regs_ctx(cm_get_context(NON_SECURE)); 230 u_register_t ns_sctlr; 231 232 psci_warmboot_entrypoint(plat_my_core_pos()); 233 234 smc_set_next_ctx(NON_SECURE); 235 236 next_smc_ctx = smc_get_next_ctx(); 237 zeromem(next_smc_ctx, sizeof(smc_ctx_t)); 238 239 copy_cpu_ctx_to_smc_stx(gpregs, 240 next_smc_ctx); 241 242 /* Temporarily set the NS bit to access NS SCTLR */ 243 write_scr(read_scr() | SCR_NS_BIT); 244 isb(); 245 ns_sctlr = read_ctx_reg(gpregs, CTX_NS_SCTLR); 246 write_sctlr(ns_sctlr); 247 isb(); 248 249 write_scr(read_scr() & ~SCR_NS_BIT); 250 isb(); 251 } 252 253 #if SP_MIN_WITH_SECURE_FIQ 254 /****************************************************************************** 255 * This function is invoked on secure interrupts. By construction of the 256 * SP_MIN, secure interrupts can only be handled when core executes in non 257 * secure state. 258 *****************************************************************************/ 259 void sp_min_fiq(void) 260 { 261 uint32_t id; 262 263 id = plat_ic_acknowledge_interrupt(); 264 sp_min_plat_fiq_handler(id); 265 plat_ic_end_of_interrupt(id); 266 } 267 #endif /* SP_MIN_WITH_SECURE_FIQ */ 268