1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <assert.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <drivers/synopsys/dw_mmc.h> 17 #include <drivers/ti/uart/uart_16550.h> 18 #include <lib/xlat_tables/xlat_tables.h> 19 20 #include "agilex_mmc.h" 21 #include "agilex_clock_manager.h" 22 #include "agilex_memory_controller.h" 23 #include "agilex_pinmux.h" 24 #include "ccu/ncore_ccu.h" 25 #include "qspi/cadence_qspi.h" 26 #include "socfpga_emac.h" 27 #include "socfpga_f2sdram_manager.h" 28 #include "socfpga_handoff.h" 29 #include "socfpga_mailbox.h" 30 #include "socfpga_private.h" 31 #include "socfpga_reset_manager.h" 32 #include "socfpga_ros.h" 33 #include "socfpga_system_manager.h" 34 #include "socfpga_vab.h" 35 #include "wdt/watchdog.h" 36 37 static struct mmc_device_info mmc_info; 38 39 const mmap_region_t agilex_plat_mmap[] = { 40 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, 41 MT_MEMORY | MT_RW | MT_NS), 42 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, 43 MT_DEVICE | MT_RW | MT_NS), 44 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, 45 MT_DEVICE | MT_RW | MT_SECURE), 46 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, 47 MT_NON_CACHEABLE | MT_RW | MT_SECURE), 48 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, 49 MT_DEVICE | MT_RW | MT_SECURE), 50 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, 51 MT_DEVICE | MT_RW | MT_NS), 52 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, 53 MT_DEVICE | MT_RW | MT_NS), 54 {0}, 55 }; 56 57 boot_source_type boot_source = BOOT_SOURCE; 58 59 void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, 60 u_register_t x2, u_register_t x4) 61 { 62 static console_t console; 63 handoff reverse_handoff_ptr; 64 65 generic_delay_timer_init(); 66 67 if (socfpga_get_handoff(&reverse_handoff_ptr)) 68 return; 69 config_pinmux(&reverse_handoff_ptr); 70 config_clkmgr_handoff(&reverse_handoff_ptr); 71 72 enable_nonsecure_access(); 73 deassert_peripheral_reset(); 74 config_hps_hs_before_warm_reset(); 75 76 watchdog_init(get_wdt_clk()); 77 78 console_16550_register(PLAT_INTEL_UART_BASE, get_uart_clk(), 79 PLAT_BAUDRATE, &console); 80 81 socfpga_delay_timer_init(); 82 init_ncore_ccu(); 83 socfpga_emac_init(); 84 init_hard_memory_controller(); 85 mailbox_init(); 86 agx_mmc_init(); 87 88 if (!intel_mailbox_is_fpga_not_ready()) { 89 socfpga_bridges_enable(SOC2FPGA_MASK | LWHPS2FPGA_MASK | 90 FPGA2SOC_MASK); 91 } 92 } 93 94 95 void bl2_el3_plat_arch_setup(void) 96 { 97 98 unsigned long offset = 0; 99 const mmap_region_t bl_regions[] = { 100 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, 101 MT_MEMORY | MT_RW | MT_SECURE), 102 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 103 MT_CODE | MT_SECURE), 104 MAP_REGION_FLAT(BL_RO_DATA_BASE, 105 BL_RO_DATA_END - BL_RO_DATA_BASE, 106 MT_RO_DATA | MT_SECURE), 107 #if USE_COHERENT_MEM_BAR 108 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, 109 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 110 MT_DEVICE | MT_RW | MT_SECURE), 111 #endif 112 {0}, 113 }; 114 115 setup_page_tables(bl_regions, agilex_plat_mmap); 116 117 /* 118 * TODO: mmu enable in latest phase 119 */ 120 // enable_mmu_el3(0); 121 122 dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk()); 123 124 mmc_info.mmc_dev_type = MMC_IS_SD; 125 mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3; 126 127 /* Request ownership and direct access to QSPI */ 128 mailbox_hps_qspi_enable(); 129 130 switch (boot_source) { 131 case BOOT_SOURCE_SDMMC: 132 NOTICE("SDMMC boot\n"); 133 dw_mmc_init(¶ms, &mmc_info); 134 socfpga_io_setup(boot_source, PLAT_SDMMC_DATA_BASE); 135 break; 136 137 case BOOT_SOURCE_QSPI: 138 NOTICE("QSPI boot\n"); 139 cad_qspi_init(0, QSPI_CONFIG_CPHA, QSPI_CONFIG_CPOL, 140 QSPI_CONFIG_CSDA, QSPI_CONFIG_CSDADS, 141 QSPI_CONFIG_CSEOT, QSPI_CONFIG_CSSOT, 0); 142 if (ros_qspi_get_ssbl_offset(&offset) != ROS_RET_OK) { 143 offset = PLAT_QSPI_DATA_BASE; 144 } 145 socfpga_io_setup(boot_source, offset); 146 break; 147 148 default: 149 ERROR("Unsupported boot source\n"); 150 panic(); 151 break; 152 } 153 } 154 155 uint32_t get_spsr_for_bl33_entry(void) 156 { 157 unsigned long el_status; 158 unsigned int mode; 159 uint32_t spsr; 160 161 /* Figure out what mode we enter the non-secure world in */ 162 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 163 el_status &= ID_AA64PFR0_ELX_MASK; 164 165 mode = (el_status) ? MODE_EL2 : MODE_EL1; 166 167 /* 168 * TODO: Consider the possibility of specifying the SPSR in 169 * the FIP ToC and allowing the platform to have a say as 170 * well. 171 */ 172 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 173 return spsr; 174 } 175 176 177 int bl2_plat_handle_post_image_load(unsigned int image_id) 178 { 179 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 180 181 assert(bl_mem_params); 182 183 #if SOCFPGA_SECURE_VAB_AUTH 184 /* 185 * VAB Authentication start here. 186 * If failed to authenticate, shall not proceed to process BL31 and hang. 187 */ 188 int ret = 0; 189 190 ret = socfpga_vab_init(image_id); 191 if (ret < 0) { 192 ERROR("SOCFPGA VAB Authentication failed\n"); 193 wfi(); 194 } 195 #endif 196 197 switch (image_id) { 198 case BL33_IMAGE_ID: 199 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 200 bl_mem_params->ep_info.spsr = get_spsr_for_bl33_entry(); 201 break; 202 default: 203 break; 204 } 205 206 return 0; 207 } 208 209 /******************************************************************************* 210 * Perform any BL3-1 platform setup code 211 ******************************************************************************/ 212 void bl2_platform_setup(void) 213 { 214 } 215