1/* 2 * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_n3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse-N3 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-N3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24.global check_erratum_neoverse_n3_3699563 25 26add_erratum_entry neoverse_n3, ERRATUM(3699563), ERRATA_N3_3699563, NO_APPLY_AT_RESET 27 28check_erratum_ls neoverse_n3, ERRATUM(3699563), CPU_REV(0, 0) 29 30cpu_reset_func_start neoverse_n3 31 /* Disable speculative loads */ 32 msr SSBS, xzr 33 34#if NEOVERSE_Nx_EXTERNAL_LLC 35 /* Some systems may have External LLC, core needs to be made aware */ 36 sysreg_bit_set NEOVERSE_N3_CPUECTLR_EL1, NEOVERSE_N3_CPUECTLR_EL1_EXTLLC_BIT 37#endif 38cpu_reset_func_end neoverse_n3 39 40 /* ---------------------------------------------------- 41 * HW will do the cache maintenance while powering down 42 * ---------------------------------------------------- 43 */ 44func neoverse_n3_core_pwr_dwn 45 /* --------------------------------------------------- 46 * Enable CPU power down bit in power control register 47 * --------------------------------------------------- 48 */ 49 sysreg_bit_set NEOVERSE_N3_CPUPWRCTLR_EL1, NEOVERSE_N3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 50 isb 51 ret 52endfunc neoverse_n3_core_pwr_dwn 53 54 /* --------------------------------------------- 55 * This function provides Neoverse-N3 specific 56 * register information for crash reporting. 57 * It needs to return with x6 pointing to 58 * a list of register names in ascii and 59 * x8 - x15 having values of registers to be 60 * reported. 61 * --------------------------------------------- 62 */ 63.section .rodata.neoverse_n3_regs, "aS" 64neoverse_n3_regs: /* The ascii list of register names to be reported */ 65 .asciz "cpuectlr_el1", "" 66 67func neoverse_n3_cpu_reg_dump 68 adr x6, neoverse_n3_regs 69 mrs x8, NEOVERSE_N3_CPUECTLR_EL1 70 ret 71endfunc neoverse_n3_cpu_reg_dump 72 73declare_cpu_ops neoverse_n3, NEOVERSE_N3_MIDR, \ 74 neoverse_n3_reset_func, \ 75 neoverse_n3_core_pwr_dwn 76