1/* 2 * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cortex_a75.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13 14.global check_erratum_cortex_a75_764081 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081 22 sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT 23workaround_reset_end cortex_a75, ERRATUM(764081) 24 25check_erratum_ls cortex_a75, ERRATUM(764081), CPU_REV(0, 0) 26 27workaround_reset_start cortex_a75, ERRATUM(790748), ERRATA_A75_790748 28 sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, (1 << 13) 29workaround_reset_end cortex_a75, ERRATUM(790748) 30 31check_erratum_ls cortex_a75, ERRATUM(790748), CPU_REV(0, 0) 32 33workaround_reset_start cortex_a75, ERRATUM(798953), ERRATA_DSU_798953 34 errata_dsu_798953_wa_impl 35workaround_reset_end cortex_a75, ERRATUM(798953) 36 37check_erratum_custom_start cortex_a75, ERRATUM(798953) 38 check_errata_dsu_798953_impl 39 ret 40check_erratum_custom_end cortex_a75, ERRATUM(798953) 41 42workaround_reset_start cortex_a75, ERRATUM(936184), ERRATA_DSU_936184 43 errata_dsu_936184_wa_impl 44workaround_reset_end cortex_a75, ERRATUM(936184) 45 46check_erratum_custom_start cortex_a75, ERRATUM(936184) 47 check_errata_dsu_936184_impl 48 ret 49check_erratum_custom_end cortex_a75, ERRATUM(936184) 50 51workaround_reset_start cortex_a75, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 52#if IMAGE_BL31 53 override_vector_table wa_cve_2017_5715_bpiall_vbar 54#endif /* IMAGE_BL31 */ 55workaround_reset_end cortex_a75, CVE(2017, 5715) 56 57check_erratum_custom_start cortex_a75, CVE(2017, 5715) 58 cpu_check_csv2 x0, 1f 59#if WORKAROUND_CVE_2017_5715 60 mov x0, #ERRATA_APPLIES 61#else 62 mov x0, #ERRATA_MISSING 63#endif 64 ret 651: 66 mov x0, #ERRATA_NOT_APPLIES 67 ret 68check_erratum_custom_end cortex_a75, CVE(2017, 5715) 69 70workaround_reset_start cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 71 sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE 72workaround_reset_end cortex_a75, CVE(2018, 3639) 73 74check_erratum_chosen cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 75 76workaround_reset_start cortex_a75, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 77#if IMAGE_BL31 78 /* Skip installing vector table again if already done for CVE(2017, 5715) */ 79 adr x0, wa_cve_2017_5715_bpiall_vbar 80 mrs x1, vbar_el3 81 cmp x0, x1 82 b.eq 1f 83 msr vbar_el3, x0 841: 85#endif /* IMAGE_BL31 */ 86workaround_reset_end cortex_a75, CVE(2022, 23960) 87 88check_erratum_custom_start cortex_a75, CVE(2022, 23960) 89#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 90 cpu_check_csv2 x0, 1f 91 mov x0, #ERRATA_APPLIES 92 ret 931: 94# if WORKAROUND_CVE_2022_23960 95 mov x0, #ERRATA_APPLIES 96# else 97 mov x0, #ERRATA_MISSING 98# endif /* WORKAROUND_CVE_2022_23960 */ 99 ret 100#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 101 mov x0, #ERRATA_MISSING 102 ret 103check_erratum_custom_end cortex_a75, CVE(2022, 23960) 104 105 /* ------------------------------------------------- 106 * The CPU Ops reset function for Cortex-A75. 107 * ------------------------------------------------- 108 */ 109 110cpu_reset_func_start cortex_a75 111#if ENABLE_FEAT_AMU 112 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 113 sysreg_bit_set actlr_el3, CORTEX_A75_ACTLR_AMEN_BIT 114 isb 115 116 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 117 sysreg_bit_set actlr_el2, CORTEX_A75_ACTLR_AMEN_BIT 118 isb 119 120 /* Enable group0 counters */ 121 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 122 msr CPUAMCNTENSET_EL0, x0 123 isb 124 125 /* Enable group1 counters */ 126 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 127 msr CPUAMCNTENSET_EL0, x0 128 /* isb included in cpu_reset_func_end macro */ 129#endif 130cpu_reset_func_end cortex_a75 131 132func check_smccc_arch_workaround_3 133 mov x0, #ERRATA_APPLIES 134 ret 135endfunc check_smccc_arch_workaround_3 136 137 /* --------------------------------------------- 138 * HW will do the cache maintenance while powering down 139 * --------------------------------------------- 140 */ 141func cortex_a75_core_pwr_dwn 142 /* --------------------------------------------- 143 * Enable CPU power down bit in power control register 144 * --------------------------------------------- 145 */ 146 sysreg_bit_set CORTEX_A75_CPUPWRCTLR_EL1, \ 147 CORTEX_A75_CORE_PWRDN_EN_MASK 148 isb 149 ret 150endfunc cortex_a75_core_pwr_dwn 151 152 /* --------------------------------------------- 153 * This function provides cortex_a75 specific 154 * register information for crash reporting. 155 * It needs to return with x6 pointing to 156 * a list of register names in ascii and 157 * x8 - x15 having values of registers to be 158 * reported. 159 * --------------------------------------------- 160 */ 161.section .rodata.cortex_a75_regs, "aS" 162cortex_a75_regs: /* The ascii list of register names to be reported */ 163 .asciz "cpuectlr_el1", "" 164 165func cortex_a75_cpu_reg_dump 166 adr x6, cortex_a75_regs 167 mrs x8, CORTEX_A75_CPUECTLR_EL1 168 ret 169endfunc cortex_a75_cpu_reg_dump 170 171declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \ 172 cortex_a75_reset_func, \ 173 check_erratum_cortex_a75_5715, \ 174 CPU_NO_EXTRA2_FUNC, \ 175 check_smccc_arch_workaround_3, \ 176 cortex_a75_core_pwr_dwn 177