1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_cortex_x3_3701769 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31cpu_reset_prologue cortex_x3 32 33workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875 34 sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22) 35workaround_reset_end cortex_x3, ERRATUM(2266875) 36 37check_erratum_ls cortex_x3, ERRATUM(2266875), CPU_REV(1, 0) 38 39workaround_reset_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506 40 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(0) 41workaround_reset_end cortex_x3, ERRATUM(2302506) 42 43check_erratum_ls cortex_x3, ERRATUM(2302506), CPU_REV(1, 1) 44 45.global erratum_cortex_x3_2313909_wa 46workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 47 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 48 * the workaround. Second call clears it to undo it. */ 49 sysreg_bit_toggle CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 50workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB 51 52check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0) 53 54workaround_reset_start cortex_x3, ERRATUM(2372204), ERRATA_X3_2372204 55 /* Set bit 40 in CPUACTLR2_EL1 */ 56 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(40) 57workaround_reset_end cortex_x3, ERRATUM(2372204) 58 59check_erratum_ls cortex_x3, ERRATUM(2372204), CPU_REV(1, 0) 60 61workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812 62 /* Disable retention control for WFI and WFE. */ 63 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 64 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3 65 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3 66 msr CORTEX_X3_CPUPWRCTLR_EL1, x0 67workaround_reset_end cortex_x3, ERRATUM(2615812) 68 69check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1) 70 71workaround_reset_start cortex_x3, ERRATUM(2641945), ERRATA_X3_2641945 72 sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) 73workaround_reset_end cortex_x3, ERRATUM(2641945) 74 75check_erratum_ls cortex_x3, ERRATUM(2641945), CPU_REV(1, 0) 76 77workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421 78 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 79 sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55 80 sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56 81workaround_reset_end cortex_x3, ERRATUM(2742421) 82 83check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1) 84 85workaround_runtime_start cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088 86 /* dsb before isb of power down sequence */ 87 dsb sy 88workaround_runtime_end cortex_x3, ERRATUM(2743088), NO_ISB 89 90check_erratum_ls cortex_x3, ERRATUM(2743088), CPU_REV(1, 1) 91 92workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509 93 /* Set CPUACTLR3_EL1 bit 47 */ 94 sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47 95workaround_reset_end cortex_x3, ERRATUM(2779509) 96 97check_erratum_ls cortex_x3, ERRATUM(2779509), CPU_REV(1, 1) 98 99add_erratum_entry cortex_x3, ERRATUM(3701769), ERRATA_X3_3701769 100 101check_erratum_ls cortex_x3, ERRATUM(3701769), CPU_REV(1, 2) 102 103workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 104#if IMAGE_BL31 105 override_vector_table wa_cve_vbar_cortex_x3 106#endif /* IMAGE_BL31 */ 107workaround_reset_end cortex_x3, CVE(2022, 23960) 108 109check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 110 111/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 112workaround_reset_start cortex_x3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 113 sysreg_bit_set CORTEX_X3_CPUECTLR_EL1, BIT(46) 114workaround_reset_end cortex_x3, CVE(2024, 5660) 115 116check_erratum_ls cortex_x3, CVE(2024, 5660), CPU_REV(1, 2) 117 118workaround_reset_start cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 119 /* --------------------------------- 120 * Sets BIT41 of CPUACTLR6_EL1 which 121 * disables L1 Data cache prefetcher 122 * --------------------------------- 123 */ 124 sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) 125workaround_reset_end cortex_x3, CVE(2024, 7881) 126 127check_erratum_chosen cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 128 129cpu_reset_func_start cortex_x3 130 /* Disable speculative loads */ 131 msr SSBS, xzr 132 enable_mpmm 133cpu_reset_func_end cortex_x3 134 135 /* ---------------------------------------------------- 136 * HW will do the cache maintenance while powering down 137 * ---------------------------------------------------- 138 */ 139func cortex_x3_core_pwr_dwn 140 apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909, NO_GET_CPU_REV 141 /* --------------------------------------------------- 142 * Enable CPU power down bit in power control register 143 * --------------------------------------------------- 144 */ 145 sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 146 apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088, NO_GET_CPU_REV 147 isb 148 ret 149endfunc cortex_x3_core_pwr_dwn 150 151 /* --------------------------------------------- 152 * This function provides Cortex-X3- 153 * specific register information for crash 154 * reporting. It needs to return with x6 155 * pointing to a list of register names in ascii 156 * and x8 - x15 having values of registers to be 157 * reported. 158 * --------------------------------------------- 159 */ 160.section .rodata.cortex_x3_regs, "aS" 161cortex_x3_regs: /* The ascii list of register names to be reported */ 162 .asciz "cpuectlr_el1", "" 163 164func cortex_x3_cpu_reg_dump 165 adr x6, cortex_x3_regs 166 mrs x8, CORTEX_X3_CPUECTLR_EL1 167 ret 168endfunc cortex_x3_cpu_reg_dump 169 170declare_cpu_ops_wa_4 cortex_x3, CORTEX_X3_MIDR, \ 171 cortex_x3_reset_func, \ 172 CPU_NO_EXTRA1_FUNC, \ 173 CPU_NO_EXTRA2_FUNC, \ 174 CPU_NO_EXTRA3_FUNC, \ 175 check_erratum_cortex_x3_7881, \ 176 cortex_x3_core_pwr_dwn 177