1# 2# Copyright (c) 2016-2025, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture feature modifiers: none by default 23ARM_ARCH_FEATURE := none 24 25# ARM Architecture major and minor versions: 8.0 by default. 26ARM_ARCH_MAJOR := 8 27ARM_ARCH_MINOR := 0 28 29# Base commit to perform code check on 30BASE_COMMIT := origin/master 31 32# Execute BL2 at EL3 33RESET_TO_BL2 := 0 34 35# Only use SP packages if SP layout JSON is defined 36BL2_ENABLE_SP_LOAD := 0 37 38# BL2 image is stored in XIP memory, for now, this option is only supported 39# when RESET_TO_BL2 is 1. 40BL2_IN_XIP_MEM := 0 41 42# Do dcache invalidate upon BL2 entry at EL3 43BL2_INV_DCACHE := 1 44 45# Select the branch protection features to use. 46BRANCH_PROTECTION := 0 47 48# By default, consider that the platform may release several CPUs out of reset. 49# The platform Makefile is free to override this value. 50COLD_BOOT_SINGLE_CPU := 0 51 52# Flag to compile in coreboot support code. Exclude by default. The coreboot 53# Makefile system will set this when compiling TF as part of a coreboot image. 54COREBOOT := 0 55 56# For Chain of Trust 57CREATE_KEYS := 1 58 59# Build flag to include AArch32 registers in cpu context save and restore during 60# world switch. This flag must be set to 0 for AArch64-only platforms. 61CTX_INCLUDE_AARCH32_REGS := 1 62 63# Include FP registers in cpu context 64CTX_INCLUDE_FPREGS := 0 65 66# Include SVE registers in cpu context 67CTX_INCLUDE_SVE_REGS := 0 68 69# Debug build 70DEBUG := 0 71 72# By default disable authenticated decryption support. 73DECRYPTION_SUPPORT := none 74 75# Build platform 76DEFAULT_PLAT := fvp 77 78# Disable the generation of the binary image (ELF only). 79DISABLE_BIN_GENERATION := 0 80 81# Enable capability to disable authentication dynamically. Only meant for 82# development platforms. 83DYN_DISABLE_AUTH := 0 84 85# Enable the Maximum Power Mitigation Mechanism on supporting cores. 86ENABLE_MPMM := 0 87 88# Enable support for powerdown abandons 89FEAT_PABANDON := 0 90 91# Flag to Enable Position Independant support (PIE) 92ENABLE_PIE := 0 93 94# Flag to enable Performance Measurement Framework 95ENABLE_PMF := 0 96 97# Flag to enable PSCI STATs functionality 98ENABLE_PSCI_STAT := 0 99 100# Flag to enable runtime instrumentation using PMF 101ENABLE_RUNTIME_INSTRUMENTATION := 0 102 103# Flag to enable stack corruption protection 104ENABLE_STACK_PROTECTOR := 0 105 106# Flag to enable exception handling in EL3 107EL3_EXCEPTION_HANDLING := 0 108 109# Flag to include all errata for all CPUs TF-A implements workarounds for 110# Its supposed to be used only for testing. 111ENABLE_ERRATA_ALL := 0 112 113# By default BL31 encryption disabled 114ENCRYPT_BL31 := 0 115 116# By default BL32 encryption disabled 117ENCRYPT_BL32 := 0 118 119# Default dummy firmware encryption key 120ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 121 122# Default dummy nonce for firmware encryption 123ENC_NONCE := 1234567890abcdef12345678 124 125# Build flag to treat usage of deprecated platform and framework APIs as error. 126ERROR_DEPRECATED := 0 127 128# Fault injection support 129FAULT_INJECTION_SUPPORT := 0 130 131# Flag to enable architectural features detection mechanism 132FEATURE_DETECTION := 0 133 134# Byte alignment that each component in FIP is aligned to 135FIP_ALIGN := 0 136 137# Default FIP file name 138FIP_NAME := fip.bin 139 140# Default FWU_FIP file name 141FWU_FIP_NAME := fwu_fip.bin 142 143# By default firmware encryption with SSK 144FW_ENC_STATUS := 0 145 146# For Chain of Trust 147GENERATE_COT := 0 148 149# Default number of 512 blocks per bitlock 150RME_GPT_BITLOCK_BLOCK := 1 151 152# Default maximum size of GPT contiguous block 153RME_GPT_MAX_BLOCK := 512 154 155# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 156# default, they are for Secure EL1. 157GICV2_G0_FOR_EL3 := 0 158 159# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled 160# by lower ELs. 161HANDLE_EA_EL3_FIRST_NS := 0 162 163# Enable Handoff protocol using transfer lists 164TRANSFER_LIST := 0 165 166# Enable HOB list to generate boot information 167HOB_LIST := 0 168 169# Enables support for the gcc compiler option "-mharden-sls=all". 170# By default, disables all SLS hardening. 171HARDEN_SLS := 0 172 173# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 174# The default value is sha256. 175HASH_ALG := sha256 176 177# Whether system coherency is managed in hardware, without explicit software 178# operations. 179HW_ASSISTED_COHERENCY := 0 180 181# Flag to enable trapping of implementation defined sytem registers 182IMPDEF_SYSREG_TRAP := 0 183 184# Set the default algorithm for the generation of Trusted Board Boot keys 185KEY_ALG := rsa 186 187# Set the default key size in case KEY_ALG is rsa 188ifeq ($(KEY_ALG),rsa) 189KEY_SIZE := 2048 190endif 191 192# Option to build TF with Measured Boot support 193MEASURED_BOOT := 0 194 195# Option to build TF with Discrete TPM support 196DISCRETE_TPM := 0 197 198# Option to enable the DICE Protection Environmnet as a Measured Boot backend 199DICE_PROTECTION_ENVIRONMENT :=0 200 201# NS timer register save and restore 202NS_TIMER_SWITCH := 0 203 204# Include lib/libc in the final image 205OVERRIDE_LIBC := 0 206 207# Build PL011 UART driver in minimal generic UART mode 208PL011_GENERIC_UART := 0 209 210# By default, consider that the platform's reset address is not programmable. 211# The platform Makefile is free to override this value. 212PROGRAMMABLE_RESET_ADDRESS := 0 213 214# Flag used to choose the power state format: Extended State-ID or Original 215PSCI_EXTENDED_STATE_ID := 0 216 217# Enable PSCI OS-initiated mode support 218PSCI_OS_INIT_MODE := 0 219 220# SMCCC_ARCH_FEATURE_AVAILABILITY support 221ARCH_FEATURE_AVAILABILITY := 0 222 223# By default, BL1 acts as the reset handler, not BL31 224RESET_TO_BL31 := 0 225 226# For Chain of Trust 227SAVE_KEYS := 0 228 229# Software Delegated Exception support 230SDEI_SUPPORT := 0 231 232# True Random Number firmware Interface support 233TRNG_SUPPORT := 0 234 235# Check to see if Errata ABI is supported 236ERRATA_ABI_SUPPORT := 0 237 238# Check to enable Errata ABI for platforms with non-arm interconnect 239ERRATA_NON_ARM_INTERCONNECT := 0 240 241# SMCCC PCI support 242SMC_PCI_SUPPORT := 0 243 244# Whether code and read-only data should be put on separate memory pages. The 245# platform Makefile is free to override this value. 246SEPARATE_CODE_AND_RODATA := 0 247 248# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 249# separate memory region, which may be discontiguous from the rest of BL31. 250SEPARATE_NOBITS_REGION := 0 251 252# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory 253# region, platform Makefile is free to override this value. 254SEPARATE_BL2_NOLOAD_REGION := 0 255 256# Put RW DATA sections (.rwdata) in a separate memory region, which may be 257# discontiguous from the rest of BL31. 258SEPARATE_RWDATA_REGION := 0 259 260# Put SIMD context data structures in a separate memory region. Platforms 261# have the choice to put it outside of default BSS region of EL3 firmware. 262SEPARATE_SIMD_SECTION := 0 263 264# If the BL31 image initialisation code is recalimed after use for the secondary 265# cores stack 266RECLAIM_INIT_CODE := 0 267 268# SPD choice 269SPD := none 270 271# Enable the Management Mode (MM)-based Secure Partition Manager implementation 272SPM_MM := 0 273 274# Use the FF-A SPMC implementation in EL3. 275SPMC_AT_EL3 := 0 276 277# Enable SEL0 SP when SPMC is enabled at EL3 278SPMC_AT_EL3_SEL0_SP :=0 279 280# Use SPM at S-EL2 as a default config for SPMD 281SPMD_SPM_AT_SEL2 := 1 282 283# Flag to introduce an infinite loop in BL1 just before it exits into the next 284# image. This is meant to help debugging the post-BL2 phase. 285SPIN_ON_BL1_EXIT := 0 286 287# Flags to build TF with Trusted Boot support 288TRUSTED_BOARD_BOOT := 0 289 290# Build option to choose whether Trusted Firmware uses Coherent memory or not. 291USE_COHERENT_MEM := 1 292 293# Build option to add debugfs support 294USE_DEBUGFS := 0 295 296# Build option to fconf based io 297ARM_IO_IN_DTB := 0 298 299# Build option to support SDEI through fconf 300SDEI_IN_FCONF := 0 301 302# Build option to support Secure Interrupt descriptors through fconf 303SEC_INT_DESC_IN_FCONF := 0 304 305# Build option to choose whether Trusted Firmware uses library at ROM 306USE_ROMLIB := 0 307 308# Build option to choose whether the xlat tables of BL images can be read-only. 309# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 310# which is the per BL-image option that actually enables the read-only tables 311# API. The reason for having this additional option is to have a common high 312# level makefile where we can check for incompatible features/build options. 313ALLOW_RO_XLAT_TABLES := 0 314 315# Chain of trust. 316COT := tbbr 317 318# Use tbbr_oid.h instead of platform_oid.h 319USE_TBBR_DEFS := 1 320 321# Whether to enable D-Cache early during warm boot. This is usually 322# applicable for platforms wherein interconnect programming is not 323# required to enable cache coherency after warm reset (eg: single cluster 324# platforms). 325WARMBOOT_ENABLE_DCACHE_EARLY := 0 326 327# Default SVE vector length to maximum architected value 328SVE_VECTOR_LEN := 2048 329 330SANITIZE_UB := off 331 332# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 333# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 334# Default: disabled 335USE_SPINLOCK_CAS := 0 336 337# Enable Link Time Optimization 338ENABLE_LTO := 0 339 340# This option will include EL2 registers in cpu context save and restore during 341# EL2 firmware entry/exit. Internal flag not meant for direct setting. 342# Use SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1 to enable 343# CTX_INCLUDE_EL2_REGS. 344CTX_INCLUDE_EL2_REGS := 0 345 346# Enable Memory tag extension which is supported for architecture greater 347# than Armv8.5-A 348# By default it is set to "no" 349SUPPORT_STACK_MEMTAG := no 350 351# Select workaround for AT speculative behaviour. 352ERRATA_SPECULATIVE_AT := 0 353 354# select workaround for SME aborting powerdown 355ERRATA_SME_POWER_DOWN := 0 356 357# Trap RAS error record access from Non secure 358RAS_TRAP_NS_ERR_REC_ACCESS := 0 359 360# Build option to create cot descriptors using fconf 361COT_DESC_IN_DTB := 0 362 363# Build option to provide OpenSSL directory path 364OPENSSL_DIR := /usr 365 366# Select the openssl binary provided in OPENSSL_DIR variable 367ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "") 368 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps 369else 370 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin 371endif 372 373# Build option to use the SP804 timer instead of the generic one 374USE_SP804_TIMER := 0 375 376# Build option to define number of firmware banks, used in firmware update 377# metadata structure. 378NR_OF_FW_BANKS := 2 379 380# Build option to define number of images in firmware bank, used in firmware 381# update metadata structure. 382NR_OF_IMAGES_IN_FW_BANK := 1 383 384# Disable Firmware update support by default 385PSA_FWU_SUPPORT := 0 386 387# Enable image description in FWU metadata by default when PSA_FWU_SUPPORT 388# is enabled. 389ifeq ($(PSA_FWU_SUPPORT),1) 390PSA_FWU_METADATA_FW_STORE_DESC := 1 391else 392PSA_FWU_METADATA_FW_STORE_DESC := 0 393endif 394 395# Dynamic Root of Trust for Measurement support 396DRTM_SUPPORT := 0 397 398# Check platform if cache management operations should be performed. 399# Disabled by default. 400CONDITIONAL_CMO := 0 401 402# By default, disable SPMD Logical partitions 403ENABLE_SPMD_LP := 0 404 405# By default, disable PSA crypto (use MbedTLS legacy crypto API). 406PSA_CRYPTO := 0 407 408# getc() support from the console(s). 409# Disabled by default because it constitutes an attack vector into TF-A. It 410# should only be enabled if there is a use case for it. 411ENABLE_CONSOLE_GETC := 0 412 413# Build option to disable EL2 when it is not used. 414# Most platforms switch from EL3 to NS-EL2 and hence the unused NS-EL2 415# functions must be enabled by platforms if they require it. 416# Disabled by default. 417INIT_UNUSED_NS_EL2 := 0 418 419# Disable including MPAM EL2 registers in context by default since currently 420# it's only enabled for NS world 421CTX_INCLUDE_MPAM_REGS := 0 422 423# Enable context memory usage reporting during BL31 setup. 424PLATFORM_REPORT_CTX_MEM_USE := 0 425 426# Enable early console 427EARLY_CONSOLE := 0 428 429# Allow platforms to save/restore DSU PMU registers over a power cycle. 430# Disabled by default and must be enabled by individual platforms. 431PRESERVE_DSU_PMU_REGS := 0 432 433# Enable RMMD to forward attestation requests from RMM to EL3. 434RMMD_ENABLE_EL3_TOKEN_SIGN := 0 435