1/* 2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78c.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20#if WORKAROUND_CVE_2022_23960 21 wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c 22#endif /* WORKAROUND_CVE_2022_23960 */ 23 24/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 25workaround_reset_start cortex_a78c, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 26 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, BIT(46) 27workaround_reset_end cortex_a78c, CVE(2024, 5660) 28 29check_erratum_ls cortex_a78c, CVE(2024, 5660), CPU_REV(0, 2) 30 31workaround_reset_start cortex_a78c, ERRATUM(1827430), ERRATA_A78C_1827430 32 /* Disable allocation of splintered pages in the L2 TLB */ 33 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN 34workaround_reset_end cortex_a78c, ERRATUM(1827430) 35 36check_erratum_ls cortex_a78c, ERRATUM(1827430), CPU_REV(0, 0) 37 38workaround_reset_start cortex_a78c, ERRATUM(1827440), ERRATA_A78C_1827440 39 /* Force Atomic Store to WB memory be done in L1 data cache */ 40 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(2) 41workaround_reset_end cortex_a78c, ERRATUM(1827440) 42 43check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0) 44 45workaround_reset_start cortex_a78c, ERRATUM(2132064), ERRATA_A78C_2132064 46 /* -------------------------------------------------------- 47 * Place the data prefetcher in the most conservative mode 48 * to reduce prefetches by writing the following bits to 49 * the value indicated: ecltr[7:6], PF_MODE = 2'b11 50 * -------------------------------------------------------- 51 */ 52 sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, (CORTEX_A78C_CPUECTLR_EL1_BIT_6 | CORTEX_A78C_CPUECTLR_EL1_BIT_7) 53workaround_reset_end cortex_a78c, ERRATUM(2132064) 54 55check_erratum_range cortex_a78c, ERRATUM(2132064), CPU_REV(0, 1), CPU_REV(0, 2) 56 57workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638 58 ldr x0, =0x5 59 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 60 ldr x0, =0x10F600E000 61 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 62 ldr x0, =0x10FF80E000 63 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 64 ldr x0, =0x80000000003FF 65 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 66workaround_reset_end cortex_a78c, ERRATUM(2242638) 67 68check_erratum_range cortex_a78c, ERRATUM(2242638), CPU_REV(0, 1), CPU_REV(0, 2) 69 70workaround_reset_start cortex_a78c, ERRATUM(2376749), ERRATA_A78C_2376749 71 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_0 72workaround_reset_end cortex_a78c, ERRATUM(2376749) 73 74check_erratum_range cortex_a78c, ERRATUM(2376749), CPU_REV(0, 1), CPU_REV(0, 2) 75 76workaround_reset_start cortex_a78c, ERRATUM(2395411), ERRATA_A78C_2395411 77 sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_40 78workaround_reset_end cortex_a78c, ERRATUM(2395411) 79 80check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2) 81 82workaround_reset_start cortex_a78c, ERRATUM(2683027), ERRATA_A78C_2683027 83 ldr x0, =0x3 84 msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 85 ldr x0, =0xEE010F10 86 msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 87 ldr x0, =0xFF1F0FFE 88 msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 89 ldr x0, =0x100000004003FF 90 msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 91workaround_reset_end cortex_a78c, ERRATUM(2683027) 92 93check_erratum_range cortex_a78c, ERRATUM(2683027), CPU_REV(0, 1), CPU_REV(0, 2) 94 95workaround_reset_start cortex_a78c, ERRATUM(2743232), ERRATA_A78C_2743232 96 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 97 sysreg_bit_set CORTEX_A78C_ACTLR5_EL1, BIT(55) 98 sysreg_bit_clear CORTEX_A78C_ACTLR5_EL1, BIT(56) 99workaround_reset_end cortex_a78c, ERRATUM(2743232) 100 101check_erratum_range cortex_a78c, ERRATUM(2743232), CPU_REV(0, 1), CPU_REV(0, 2) 102 103workaround_runtime_start cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121 104 /* dsb before isb of power down sequence */ 105 dsb sy 106workaround_runtime_end cortex_a78c, ERRATUM(2772121) 107 108check_erratum_ls cortex_a78c, ERRATUM(2772121), CPU_REV(0, 2) 109 110workaround_reset_start cortex_a78c, ERRATUM(2779484), ERRATA_A78C_2779484 111 sysreg_bit_set CORTEX_A78C_ACTLR3_EL1, BIT(47) 112workaround_reset_end cortex_a78c, ERRATUM(2779484) 113 114check_erratum_range cortex_a78c, ERRATUM(2779484), CPU_REV(0, 1), CPU_REV(0, 2) 115 116check_erratum_chosen cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 117 118workaround_reset_start cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 119#if IMAGE_BL31 120 /* 121 * The Cortex-A78c generic vectors are overridden to apply errata 122 * mitigation on exception entry from lower ELs. 123 */ 124 override_vector_table wa_cve_vbar_cortex_a78c 125#endif /* IMAGE_BL31 */ 126workaround_reset_end cortex_a78c, CVE(2022, 23960) 127 128cpu_reset_func_start cortex_a78c 129cpu_reset_func_end cortex_a78c 130 131 /* ---------------------------------------------------- 132 * HW will do the cache maintenance while powering down 133 * ---------------------------------------------------- 134 */ 135func cortex_a78c_core_pwr_dwn 136 /* --------------------------------------------------- 137 * Enable CPU power down bit in power control register 138 * --------------------------------------------------- 139 */ 140 sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 141 142 apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121, NO_GET_CPU_REV 143 144 isb 145 ret 146endfunc cortex_a78c_core_pwr_dwn 147 148 /* --------------------------------------------- 149 * This function provides cortex_a78c specific 150 * register information for crash reporting. 151 * It needs to return with x6 pointing to 152 * a list of register names in ascii and 153 * x8 - x15 having values of registers to be 154 * reported. 155 * --------------------------------------------- 156 */ 157.section .rodata.cortex_a78c_regs, "aS" 158cortex_a78c_regs: /* The ascii list of register names to be reported */ 159 .asciz "cpuectlr_el1", "" 160 161func cortex_a78c_cpu_reg_dump 162 adr x6, cortex_a78c_regs 163 mrs x8, CORTEX_A78C_CPUECTLR_EL1 164 ret 165endfunc cortex_a78c_cpu_reg_dump 166 167declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ 168 cortex_a78c_reset_func, \ 169 cortex_a78c_core_pwr_dwn 170