1 /* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <common/interrupt_props.h> 15 #include <drivers/arm/gic_common.h> 16 #include <drivers/arm/gicv2.h> 17 #include <lib/spinlock.h> 18 19 #include "../common/gic_common_private.h" 20 #include "gicv2_private.h" 21 22 static const gicv2_driver_data_t *driver_data; 23 24 /* 25 * Spinlock to guard registers needing read-modify-write. APIs protected by this 26 * spinlock are used either at boot time (when only a single CPU is active), or 27 * when the system is fully coherent. 28 */ 29 static spinlock_t gic_lock; 30 31 /******************************************************************************* 32 * Enable secure interrupts and use FIQs to route them. Disable legacy bypass 33 * and set the priority mask register to allow all interrupts to trickle in. 34 ******************************************************************************/ 35 void gicv2_cpuif_enable(void) 36 { 37 unsigned int val; 38 39 assert(driver_data != NULL); 40 assert(driver_data->gicc_base != 0U); 41 42 /* 43 * Enable the Group 0 interrupts, FIQEn and disable Group 0/1 44 * bypass. 45 */ 46 val = CTLR_ENABLE_G0_BIT | FIQ_EN_BIT | FIQ_BYP_DIS_GRP0; 47 val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; 48 49 /* Program the idle priority in the PMR */ 50 gicc_write_pmr(driver_data->gicc_base, GIC_PRI_MASK); 51 gicc_write_ctlr(driver_data->gicc_base, val); 52 } 53 54 /******************************************************************************* 55 * Place the cpu interface in a state where it can never make a cpu exit wfi as 56 * as result of an asserted interrupt. This is critical for powering down a cpu 57 ******************************************************************************/ 58 void gicv2_cpuif_disable(void) 59 { 60 unsigned int val; 61 62 assert(driver_data != NULL); 63 assert(driver_data->gicc_base != 0U); 64 65 /* Disable secure, non-secure interrupts and disable their bypass */ 66 val = gicc_read_ctlr(driver_data->gicc_base); 67 val &= ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT); 68 val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; 69 val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; 70 gicc_write_ctlr(driver_data->gicc_base, val); 71 } 72 73 /******************************************************************************* 74 * Per cpu gic distributor setup which will be done by all cpus after a cold 75 * boot/hotplug. This marks out the secure SPIs and PPIs & enables them. 76 ******************************************************************************/ 77 void gicv2_pcpu_distif_init(void) 78 { 79 unsigned int ctlr; 80 81 assert(driver_data != NULL); 82 assert(driver_data->gicd_base != 0U); 83 84 gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base, 85 driver_data->interrupt_props, 86 driver_data->interrupt_props_num); 87 88 /* Enable G0 interrupts if not already */ 89 ctlr = gicd_read_ctlr(driver_data->gicd_base); 90 if ((ctlr & CTLR_ENABLE_G0_BIT) == 0U) { 91 gicd_write_ctlr(driver_data->gicd_base, 92 ctlr | CTLR_ENABLE_G0_BIT); 93 } 94 } 95 96 /******************************************************************************* 97 * Global gic distributor init which will be done by the primary cpu after a 98 * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It 99 * then enables the secure GIC distributor interface. 100 ******************************************************************************/ 101 void gicv2_distif_init(void) 102 { 103 unsigned int ctlr; 104 105 assert(driver_data != NULL); 106 assert(driver_data->gicd_base != 0U); 107 108 /* Disable the distributor before going further */ 109 ctlr = gicd_read_ctlr(driver_data->gicd_base); 110 gicd_write_ctlr(driver_data->gicd_base, 111 ctlr & ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT)); 112 113 /* Set the default attribute of all SPIs */ 114 gicv2_spis_configure_defaults(driver_data->gicd_base); 115 116 gicv2_secure_spis_configure_props(driver_data->gicd_base, 117 driver_data->interrupt_props, 118 driver_data->interrupt_props_num); 119 120 121 /* Re-enable the secure SPIs now that they have been configured */ 122 gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT); 123 } 124 125 /******************************************************************************* 126 * Initialize the ARM GICv2 driver with the provided platform inputs 127 ******************************************************************************/ 128 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data) 129 { 130 unsigned int gic_version; 131 132 assert(plat_driver_data != NULL); 133 assert(plat_driver_data->gicd_base != 0U); 134 assert(plat_driver_data->gicc_base != 0U); 135 136 assert(plat_driver_data->interrupt_props_num > 0 ? 137 plat_driver_data->interrupt_props != NULL : 1); 138 139 /* Ensure that this is a GICv2 system */ 140 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 141 gic_version = (gic_version >> PIDR2_ARCH_REV_SHIFT) 142 & PIDR2_ARCH_REV_MASK; 143 144 /* 145 * GICv1 with security extension complies with trusted firmware 146 * GICv2 driver as far as virtualization and few tricky power 147 * features are not used. GICv2 features that are not supported 148 * by GICv1 with Security Extensions are: 149 * - virtual interrupt support. 150 * - wake up events. 151 * - writeable GIC state register (for power sequences) 152 * - interrupt priority drop. 153 * - interrupt signal bypass. 154 */ 155 assert((gic_version == ARCH_REV_GICV2) || 156 (gic_version == ARCH_REV_GICV1)); 157 158 driver_data = plat_driver_data; 159 160 /* 161 * The GIC driver data is initialized by the primary CPU with caches 162 * enabled. When the secondary CPU boots up, it initializes the 163 * GICC/GICR interface with the caches disabled. Hence flush the 164 * driver_data to ensure coherency. This is not required if the 165 * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY 166 * enabled. 167 */ 168 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 169 flush_dcache_range((uintptr_t) &driver_data, sizeof(driver_data)); 170 flush_dcache_range((uintptr_t) driver_data, sizeof(*driver_data)); 171 #endif 172 INFO("ARM GICv2 driver initialized\n"); 173 } 174 175 /****************************************************************************** 176 * This function returns whether FIQ is enabled in the GIC CPU interface. 177 *****************************************************************************/ 178 unsigned int gicv2_is_fiq_enabled(void) 179 { 180 unsigned int gicc_ctlr; 181 182 assert(driver_data != NULL); 183 assert(driver_data->gicc_base != 0U); 184 185 gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base); 186 return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1U; 187 } 188 189 /******************************************************************************* 190 * This function returns the type of the highest priority pending interrupt at 191 * the GIC cpu interface. The return values can be one of the following : 192 * PENDING_G1_INTID : The interrupt type is non secure Group 1. 193 * 0 - 1019 : The interrupt type is secure Group 0. 194 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 195 * sufficient priority to be signaled 196 ******************************************************************************/ 197 unsigned int gicv2_get_pending_interrupt_type(void) 198 { 199 assert(driver_data != NULL); 200 assert(driver_data->gicc_base != 0U); 201 202 return gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; 203 } 204 205 /******************************************************************************* 206 * This function returns the id of the highest priority pending interrupt at 207 * the GIC cpu interface. GIC_SPURIOUS_INTERRUPT is returned when there is no 208 * interrupt pending. 209 ******************************************************************************/ 210 unsigned int gicv2_get_pending_interrupt_id(void) 211 { 212 unsigned int id; 213 214 assert(driver_data != NULL); 215 assert(driver_data->gicc_base != 0U); 216 217 id = gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; 218 219 /* 220 * Find out which non-secure interrupt it is under the assumption that 221 * the GICC_CTLR.AckCtl bit is 0. 222 */ 223 if (id == PENDING_G1_INTID) { 224 id = gicc_read_ahppir(driver_data->gicc_base) & INT_ID_MASK; 225 } 226 return id; 227 } 228 229 /******************************************************************************* 230 * This functions reads the GIC cpu interface Interrupt Acknowledge register 231 * to start handling the pending secure 0 interrupt. It returns the 232 * contents of the IAR. 233 ******************************************************************************/ 234 unsigned int gicv2_acknowledge_interrupt(void) 235 { 236 assert(driver_data != NULL); 237 assert(driver_data->gicc_base != 0U); 238 239 return gicc_read_IAR(driver_data->gicc_base); 240 } 241 242 /******************************************************************************* 243 * This functions writes the GIC cpu interface End Of Interrupt register with 244 * the passed value to finish handling the active secure group 0 interrupt. 245 ******************************************************************************/ 246 void gicv2_end_of_interrupt(unsigned int id) 247 { 248 assert(driver_data != NULL); 249 assert(driver_data->gicc_base != 0U); 250 251 /* 252 * Ensure the write to peripheral registers are *complete* before the write 253 * to GIC_EOIR. 254 * 255 * Note: The completion guarantee depends on various factors of system design 256 * and the barrier is the best core can do by which execution of further 257 * instructions waits till the barrier is alive. 258 */ 259 dsbishst(); 260 gicc_write_EOIR(driver_data->gicc_base, id); 261 } 262 263 /******************************************************************************* 264 * This function returns the type of the interrupt id depending upon the group 265 * this interrupt has been configured under by the interrupt controller i.e. 266 * group0 secure or group1 non secure. It returns zero for Group 0 secure and 267 * one for Group 1 non secure interrupt. 268 ******************************************************************************/ 269 unsigned int gicv2_get_interrupt_group(unsigned int id) 270 { 271 assert(driver_data != NULL); 272 assert(driver_data->gicd_base != 0U); 273 274 return gicd_get_igroupr(driver_data->gicd_base, id); 275 } 276 277 /******************************************************************************* 278 * This function returns the priority of the interrupt the processor is 279 * currently servicing. 280 ******************************************************************************/ 281 unsigned int gicv2_get_running_priority(void) 282 { 283 assert(driver_data != NULL); 284 assert(driver_data->gicc_base != 0U); 285 286 return gicc_read_rpr(driver_data->gicc_base); 287 } 288 289 /******************************************************************************* 290 * This function sets the GICv2 target mask pattern for the current PE. The PE 291 * target mask is used to translate linear PE index (returned by platform core 292 * position) to a bit mask used when targeting interrupts to a PE (for example 293 * when raising SGIs and routing SPIs). 294 ******************************************************************************/ 295 void gicv2_set_pe_target_mask(unsigned int proc_num) 296 { 297 assert(driver_data != NULL); 298 assert(driver_data->gicd_base != 0U); 299 assert(driver_data->target_masks != NULL); 300 assert(proc_num < GICV2_MAX_TARGET_PE); 301 assert(proc_num < driver_data->target_masks_num); 302 303 /* Return if the target mask is already populated */ 304 if (driver_data->target_masks[proc_num] != 0U) { 305 return; 306 } 307 /* 308 * Update target register corresponding to this CPU and flush for it to 309 * be visible to other CPUs. 310 */ 311 if (driver_data->target_masks[proc_num] == 0U) { 312 driver_data->target_masks[proc_num] = 313 gicv2_get_cpuif_id(driver_data->gicd_base); 314 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 315 /* 316 * PEs only update their own masks. Primary updates it with 317 * caches on. But because secondaries does it with caches off, 318 * all updates go to memory directly, and there's no danger of 319 * secondaries overwriting each others' mask, despite 320 * target_masks[] not being cache line aligned. 321 */ 322 flush_dcache_range((uintptr_t) 323 &driver_data->target_masks[proc_num], 324 sizeof(driver_data->target_masks[proc_num])); 325 #endif 326 } 327 } 328 329 /******************************************************************************* 330 * This function returns the active status of the interrupt (either because the 331 * state is active, or active and pending). 332 ******************************************************************************/ 333 unsigned int gicv2_get_interrupt_active(unsigned int id) 334 { 335 assert(driver_data != NULL); 336 assert(driver_data->gicd_base != 0U); 337 assert(id <= MAX_SPI_ID); 338 339 return gicd_get_isactiver(driver_data->gicd_base, id); 340 } 341 342 /******************************************************************************* 343 * This function enables the interrupt identified by id. 344 ******************************************************************************/ 345 void gicv2_enable_interrupt(unsigned int id) 346 { 347 assert(driver_data != NULL); 348 assert(driver_data->gicd_base != 0U); 349 assert(id <= MAX_SPI_ID); 350 351 /* 352 * Ensure that any shared variable updates depending on out of band 353 * interrupt trigger are observed before enabling interrupt. 354 */ 355 dsbishst(); 356 gicd_set_isenabler(driver_data->gicd_base, id); 357 } 358 359 /******************************************************************************* 360 * This function disables the interrupt identified by id. 361 ******************************************************************************/ 362 void gicv2_disable_interrupt(unsigned int id) 363 { 364 assert(driver_data != NULL); 365 assert(driver_data->gicd_base != 0U); 366 assert(id <= MAX_SPI_ID); 367 368 /* 369 * Disable interrupt, and ensure that any shared variable updates 370 * depending on out of band interrupt trigger are observed afterwards. 371 */ 372 gicd_set_icenabler(driver_data->gicd_base, id); 373 dsbishst(); 374 } 375 376 /******************************************************************************* 377 * This function sets the interrupt priority as supplied for the given interrupt 378 * id. 379 ******************************************************************************/ 380 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority) 381 { 382 assert(driver_data != NULL); 383 assert(driver_data->gicd_base != 0U); 384 assert(id <= MAX_SPI_ID); 385 386 gicd_set_ipriorityr(driver_data->gicd_base, id, priority); 387 } 388 389 /******************************************************************************* 390 * This function assigns group for the interrupt identified by id. The group can 391 * be any of GICV2_INTR_GROUP* 392 ******************************************************************************/ 393 void gicv2_set_interrupt_group(unsigned int id, unsigned int group) 394 { 395 assert(driver_data != NULL); 396 assert(driver_data->gicd_base != 0U); 397 assert(id <= MAX_SPI_ID); 398 399 /* Serialize read-modify-write to Distributor registers */ 400 spin_lock(&gic_lock); 401 switch (group) { 402 case GICV2_INTR_GROUP1: 403 gicd_set_igroupr(driver_data->gicd_base, id); 404 break; 405 case GICV2_INTR_GROUP0: 406 gicd_clr_igroupr(driver_data->gicd_base, id); 407 break; 408 default: 409 assert(false); 410 break; 411 } 412 spin_unlock(&gic_lock); 413 } 414 415 /******************************************************************************* 416 * This function raises the specified SGI to requested targets. 417 * 418 * The proc_num parameter must be the linear index of the target PE in the 419 * system. 420 ******************************************************************************/ 421 void gicv2_raise_sgi(int sgi_num, bool ns, int proc_num) 422 { 423 unsigned int sgir_val, target; 424 425 assert(driver_data != NULL); 426 assert(proc_num >= 0); 427 assert(proc_num < (int)GICV2_MAX_TARGET_PE); 428 assert(driver_data->gicd_base != 0U); 429 430 /* 431 * Target masks array must have been supplied, and the core position 432 * should be valid. 433 */ 434 assert(driver_data->target_masks != NULL); 435 assert(proc_num < (int)driver_data->target_masks_num); 436 437 /* Don't raise SGI if the mask hasn't been populated */ 438 target = driver_data->target_masks[proc_num]; 439 assert(target != 0U); 440 441 sgir_val = GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC, target, ns, sgi_num); 442 443 /* 444 * Ensure that any shared variable updates depending on out of band 445 * interrupt trigger are observed before raising SGI. 446 */ 447 dsbishst(); 448 gicd_write_sgir(driver_data->gicd_base, sgir_val); 449 } 450 451 /******************************************************************************* 452 * This function sets the interrupt routing for the given SPI interrupt id. 453 * The interrupt routing is specified in routing mode. The proc_num parameter is 454 * linear index of the PE to target SPI. When proc_num < 0, the SPI may target 455 * all PEs. 456 ******************************************************************************/ 457 void gicv2_set_spi_routing(unsigned int id, int proc_num) 458 { 459 unsigned int target; 460 461 assert(driver_data != NULL); 462 assert(driver_data->gicd_base != 0U); 463 464 assert((id >= MIN_SPI_ID) && (id <= MAX_SPI_ID)); 465 466 /* 467 * Target masks array must have been supplied, and the core position 468 * should be valid. 469 */ 470 assert(driver_data->target_masks != NULL); 471 assert(proc_num < (int)GICV2_MAX_TARGET_PE); 472 assert(driver_data->target_masks_num < INT_MAX); 473 assert(proc_num < (int)driver_data->target_masks_num); 474 475 if (proc_num < 0) { 476 /* Target all PEs */ 477 target = GIC_TARGET_CPU_MASK; 478 } else { 479 /* Don't route interrupt if the mask hasn't been populated */ 480 target = driver_data->target_masks[proc_num]; 481 assert(target != 0U); 482 } 483 484 gicd_set_itargetsr(driver_data->gicd_base, id, target); 485 } 486 487 /******************************************************************************* 488 * This function clears the pending status of an interrupt identified by id. 489 ******************************************************************************/ 490 void gicv2_clear_interrupt_pending(unsigned int id) 491 { 492 assert(driver_data != NULL); 493 assert(driver_data->gicd_base != 0U); 494 495 /* SGIs can't be cleared pending */ 496 assert(id >= MIN_PPI_ID); 497 498 /* 499 * Clear pending interrupt, and ensure that any shared variable updates 500 * depending on out of band interrupt trigger are observed afterwards. 501 */ 502 gicd_set_icpendr(driver_data->gicd_base, id); 503 dsbishst(); 504 } 505 506 /******************************************************************************* 507 * This function sets the pending status of an interrupt identified by id. 508 ******************************************************************************/ 509 void gicv2_set_interrupt_pending(unsigned int id) 510 { 511 assert(driver_data != NULL); 512 assert(driver_data->gicd_base != 0U); 513 514 /* SGIs can't be cleared pending */ 515 assert(id >= MIN_PPI_ID); 516 517 /* 518 * Ensure that any shared variable updates depending on out of band 519 * interrupt trigger are observed before setting interrupt pending. 520 */ 521 dsbishst(); 522 gicd_set_ispendr(driver_data->gicd_base, id); 523 } 524 525 /******************************************************************************* 526 * This function sets the PMR register with the supplied value. Returns the 527 * original PMR. 528 ******************************************************************************/ 529 unsigned int gicv2_set_pmr(unsigned int mask) 530 { 531 unsigned int old_mask; 532 533 assert(driver_data != NULL); 534 assert(driver_data->gicc_base != 0U); 535 536 old_mask = gicc_read_pmr(driver_data->gicc_base); 537 538 /* 539 * Order memory updates w.r.t. PMR write, and ensure they're visible 540 * before potential out of band interrupt trigger because of PMR update. 541 */ 542 dmbishst(); 543 gicc_write_pmr(driver_data->gicc_base, mask); 544 dsbishst(); 545 546 return old_mask; 547 } 548 549 /******************************************************************************* 550 * This function updates single interrupt configuration to be level/edge 551 * triggered 552 ******************************************************************************/ 553 void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg) 554 { 555 gicd_set_icfgr(driver_data->gicd_base, id, cfg); 556 } 557