1 /* 2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3 * Copyright (c) 2025, Altera Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SOCFPGA_FCS_H 9 #define SOCFPGA_FCS_H 10 11 /* FCS Definitions */ 12 13 #define FCS_RANDOM_WORD_SIZE 8U 14 #define FCS_PROV_DATA_WORD_SIZE 44U 15 #define FCS_SHA384_WORD_SIZE 12U 16 17 #define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U) 18 #define FCS_RANDOM_EXT_MAX_WORD_SIZE 1020U 19 #define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U) 20 #define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U) 21 22 #define FCS_RANDOM_EXT_OFFSET 3 23 24 #define FCS_MODE_DECRYPT 0x0 25 #define FCS_MODE_ENCRYPT 0x1 26 #define FCS_ENCRYPTION_DATA_0 0x10100 27 #define FCS_DECRYPTION_DATA_0 0x10102 28 #define FCS_OWNER_ID_OFFSET 0xC 29 #define FCS_CRYPTION_CRYPTO_HEADER 0x07000000 30 #define FCS_CRYPTION_RESP_WORD_SIZE 4U 31 #define FCS_CRYPTION_RESP_SIZE_OFFSET 3U 32 33 #define PSGSIGMA_TEARDOWN_MAGIC 0xB852E2A4 34 #define PSGSIGMA_SESSION_ID_ONE 0x1 35 #define PSGSIGMA_UNKNOWN_SESSION 0xFFFFFFFF 36 37 #define RESERVED_AS_ZERO 0x0 38 /* FCS Single cert */ 39 40 #define FCS_BIG_CNTR_SEL 0x1 41 42 #define FCS_SVN_CNTR_0_SEL 0x2 43 #define FCS_SVN_CNTR_1_SEL 0x3 44 #define FCS_SVN_CNTR_2_SEL 0x4 45 #define FCS_SVN_CNTR_3_SEL 0x5 46 47 #define FCS_BIG_CNTR_VAL_MAX 495U 48 #define FCS_SVN_CNTR_VAL_MAX 64U 49 50 /* FCS Attestation Cert Request Parameter */ 51 52 #define FCS_ATTEST_FIRMWARE_CERT 0x01 53 #define FCS_ATTEST_DEV_ID_SELF_SIGN_CERT 0x02 54 #define FCS_ATTEST_DEV_ID_ENROLL_CERT 0x04 55 #define FCS_ATTEST_ENROLL_SELF_SIGN_CERT 0x08 56 #define FCS_ATTEST_ALIAS_CERT 0x10 57 #define FCS_ATTEST_CERT_MAX_REQ_PARAM 0xFF 58 59 /* FCS Crypto Service */ 60 61 #define FCS_CS_KEY_OBJ_MAX_WORD_SIZE 88U 62 #define FCS_CS_KEY_INFO_MAX_WORD_SIZE 36U 63 #define FCS_CS_KEY_RESP_STATUS_MASK 0xFF 64 #define FCS_CS_KEY_RESP_STATUS_OFFSET 16U 65 66 #define FCS_CS_FIELD_SIZE_MASK 0xFFFF 67 #define FCS_CS_FIELD_FLAG_OFFSET 24 68 #define FCS_CS_FIELD_FLAG_INIT BIT(0) 69 #define FCS_CS_FIELD_FLAG_UPDATE BIT(1) 70 #define FCS_CS_FIELD_FLAG_FINALIZE BIT(2) 71 72 #define FCS_AES_MAX_DATA_SIZE 0x10000000 /* 256 MB */ 73 #define FCS_AES_MIN_DATA_SIZE 0x20 /* 32 Byte */ 74 #define FCS_AES_CMD_MAX_WORD_SIZE 15U 75 76 #define FCS_MAX_DATA_SIZE 0x20000000 /* 512 MB */ 77 #define FCS_MIN_DATA_SIZE 0x8 /* 8 Bytes */ 78 79 #define FCS_GET_DIGEST_CMD_MAX_WORD_SIZE 7U 80 #define FCS_GET_DIGEST_RESP_MAX_WORD_SIZE 19U 81 #define FCS_MAC_VERIFY_CMD_MAX_WORD_SIZE 23U 82 #define FCS_MAC_VERIFY_RESP_MAX_WORD_SIZE 4U 83 #define FCS_SHA_HMAC_CRYPTO_PARAM_SIZE_OFFSET 8U 84 85 #define FCS_ECDSA_GET_PUBKEY_MAX_WORD_SIZE 5U 86 #define FCS_ECDSA_SHA2_DATA_SIGN_CMD_MAX_WORD_SIZE 7U 87 #define FCS_ECDSA_SHA2_DATA_SIG_VERIFY_CMD_MAX_WORD_SIZE 43U 88 #define FCS_ECDSA_HASH_SIGN_CMD_MAX_WORD_SIZE 17U 89 #define FCS_ECDSA_HASH_SIG_VERIFY_CMD_MAX_WORD_SIZE 52U 90 #define FCS_ECDH_REQUEST_CMD_MAX_WORD_SIZE 29U 91 92 #define FCS_CRYPTO_ECB_BUFFER_SIZE 12U 93 #define FCS_CRYPTO_CBC_CTR_BUFFER_SIZE 28U 94 #define FCS_CRYPTO_BLOCK_MODE_MASK 0x07 95 #define FCS_CRYPTO_ECB_MODE 0x00 96 #define FCS_CRYPTO_CBC_MODE 0x01 97 #define FCS_CRYPTO_CTR_MODE 0x02 98 #define FCS_CRYPTO_GCM_MODE 0x03 99 #define FCS_CRYPTO_GCM_GHASH_MODE 0x04 100 101 #define FCS_HKDF_REQUEST_DATA_SIZE 512U 102 #define FCS_HKDF_KEY_OBJ_MAX_SIZE 352U 103 #define FCS_HKDF_KEY_DATA_SIZE 168U 104 #define FCS_HKDF_STEP0_1_KEY_OBJ_SIZE_BITS 384U 105 #define FCS_HKDF_STEP2_KEY_OBJ_SIZE_BITS 256U 106 #define FCS_HKDF_INPUT_BLOCK_SIZE 80U 107 #define FCS_HKDF_SHA2_384_KEY_DATA_SIZE 48U 108 109 /* FCS Payload Structure */ 110 typedef struct fcs_rng_payload_t { 111 uint32_t session_id; 112 uint32_t context_id; 113 uint32_t crypto_header; 114 uint32_t size; 115 } fcs_rng_payload; 116 117 typedef struct fcs_encrypt_payload_t { 118 uint32_t first_word; 119 uint32_t src_addr; 120 uint32_t src_size; 121 uint32_t dst_addr; 122 uint32_t dst_size; 123 } fcs_encrypt_payload; 124 125 typedef struct fcs_decrypt_payload_t { 126 uint32_t first_word; 127 uint32_t owner_id[2]; 128 uint32_t src_addr; 129 uint32_t src_size; 130 uint32_t dst_addr; 131 uint32_t dst_size; 132 } fcs_decrypt_payload; 133 134 typedef struct fcs_encrypt_ext_payload_t { 135 uint32_t session_id; 136 uint32_t context_id; 137 uint32_t crypto_header; 138 uint32_t src_addr; 139 uint32_t src_size; 140 uint32_t dst_addr; 141 uint32_t dst_size; 142 } fcs_encrypt_ext_payload; 143 144 typedef struct fcs_decrypt_ext_payload_t { 145 uint32_t session_id; 146 uint32_t context_id; 147 uint32_t crypto_header; 148 uint32_t owner_id[2]; 149 uint32_t src_addr; 150 uint32_t src_size; 151 uint32_t dst_addr; 152 uint32_t dst_size; 153 } fcs_decrypt_ext_payload; 154 155 typedef struct psgsigma_teardown_msg_t { 156 uint32_t reserved_word; 157 uint32_t magic_word; 158 uint32_t session_id; 159 } psgsigma_teardown_msg; 160 161 typedef struct fcs_cntr_set_preauth_payload_t { 162 uint32_t first_word; 163 uint32_t counter_value; 164 } fcs_cntr_set_preauth_payload; 165 166 typedef struct fcs_cs_key_payload_t { 167 uint32_t session_id; 168 uint32_t reserved0; 169 uint32_t reserved1; 170 uint32_t key_id; 171 } fcs_cs_key_payload; 172 173 typedef struct fcs_crypto_service_data_t { 174 uint32_t session_id; 175 uint32_t context_id; 176 uint32_t key_id; 177 uint32_t crypto_param_size; 178 uint64_t crypto_param; 179 uint8_t is_updated; 180 } fcs_crypto_service_data; 181 182 typedef struct fcs_crypto_service_aes_data_t { 183 uint32_t session_id; 184 uint32_t context_id; 185 uint32_t param_size; 186 uint32_t key_id; 187 uint32_t crypto_param[7]; 188 uint8_t is_updated; 189 } fcs_crypto_service_aes_data; 190 191 /* Functions Definitions */ 192 193 uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size, 194 uint32_t *mbox_error); 195 int intel_fcs_random_number_gen_ext(uint32_t session_id, uint32_t context_id, 196 uint32_t size, uint32_t *send_id); 197 uint32_t intel_fcs_send_cert(uint32_t smc_fid, uint32_t trans_id, 198 uint64_t addr, uint64_t size, 199 uint32_t *send_id); 200 uint32_t intel_fcs_get_provision_data(uint32_t *send_id); 201 uint32_t intel_fcs_cntr_set_preauth(uint32_t smc_fid, uint32_t trans_id, 202 uint8_t counter_type, 203 int32_t counter_value, 204 uint32_t test_bit, 205 uint32_t *mbox_error); 206 uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size, 207 uint32_t dst_addr, uint32_t dst_size, 208 uint32_t *send_id); 209 210 uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size, 211 uint32_t dst_addr, uint32_t dst_size, 212 uint32_t *send_id); 213 214 int intel_fcs_encryption_ext(uint32_t smc_fid, uint32_t trans_id, 215 uint32_t session_id, uint32_t context_id, 216 uint32_t src_addr, uint32_t src_size, 217 uint32_t dst_addr, uint32_t *dst_size, 218 uint32_t *mbox_error, uint32_t smmu_src_addr, 219 uint32_t smmu_dst_addr); 220 int intel_fcs_decryption_ext(uint32_t smc_fid, uint32_t trans_id, 221 uint32_t sesion_id, uint32_t context_id, 222 uint32_t src_addr, uint32_t src_size, 223 uint32_t dst_addr, uint32_t *dst_size, 224 uint32_t *mbox_error, uint64_t owner_id, 225 uint32_t smmu_src_addr, uint32_t smmu_dst_addr); 226 227 int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error); 228 int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error); 229 int intel_fcs_attestation_subkey(uint64_t src_addr, uint32_t src_size, 230 uint64_t dst_addr, uint32_t *dst_size, 231 uint32_t *mbox_error); 232 int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size, 233 uint64_t dst_addr, uint32_t *dst_size, 234 uint32_t *mbox_error); 235 uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, 236 uint32_t *mbox_error); 237 238 int intel_fcs_create_cert_on_reload(uint32_t smc_fid, uint32_t trans_id, 239 uint32_t cert_request, uint32_t *mbox_error); 240 int intel_fcs_get_attestation_cert(uint32_t smc_fid, uint32_t trans_id, 241 uint32_t cert_request, uint64_t dst_addr, 242 uint32_t *dst_size, uint32_t *mbox_error); 243 244 int intel_fcs_open_crypto_service_session(uint32_t *session_id, 245 uint32_t *mbox_error); 246 int intel_fcs_close_crypto_service_session(uint32_t session_id, 247 uint32_t *mbox_error); 248 249 int intel_fcs_import_crypto_service_key(uint64_t src_addr, uint32_t src_size, 250 uint32_t *mbox_error); 251 int intel_fcs_export_crypto_service_key(uint32_t session_id, uint32_t key_id, 252 uint64_t dst_addr, uint32_t *dst_size, 253 uint32_t *mbox_error); 254 int intel_fcs_remove_crypto_service_key(uint32_t session_id, uint32_t key_id, 255 uint32_t *mbox_error); 256 int intel_fcs_get_crypto_service_key_info(uint32_t session_id, uint32_t key_id, 257 uint64_t dst_addr, uint32_t *dst_size, 258 uint32_t *mbox_error); 259 260 int intel_fcs_get_digest_init(uint32_t session_id, uint32_t context_id, 261 uint32_t key_id, uint32_t param_size, 262 uint64_t param_data, uint32_t *mbox_error); 263 int intel_fcs_get_digest_update_finalize(uint32_t smc_fid, uint32_t trans_id, 264 uint32_t session_id, uint32_t context_id, 265 uint32_t src_addr, uint32_t src_size, 266 uint64_t dst_addr, uint32_t *dst_size, 267 uint8_t is_finalised, uint32_t *mbox_error, 268 uint32_t smmu_src_addr); 269 int intel_fcs_get_digest_smmu_update_finalize(uint32_t session_id, uint32_t context_id, 270 uint32_t src_addr, uint32_t src_size, 271 uint64_t dst_addr, uint32_t *dst_size, 272 uint8_t is_finalised, uint32_t *mbox_error, 273 uint32_t *send_id); 274 275 int intel_fcs_mac_verify_init(uint32_t session_id, uint32_t context_id, 276 uint32_t key_id, uint32_t param_size, 277 uint64_t param_data, uint32_t *mbox_error); 278 int intel_fcs_mac_verify_update_finalize(uint32_t smc_fid, uint32_t trans_id, 279 uint32_t session_id, uint32_t context_id, 280 uint32_t src_addr, uint32_t src_size, 281 uint64_t dst_addr, uint32_t *dst_size, 282 uint32_t data_size, uint8_t is_finalised, 283 uint32_t *mbox_error, uint64_t smmu_src_addr); 284 int intel_fcs_mac_verify_smmu_update_finalize(uint32_t session_id, uint32_t context_id, 285 uint32_t src_addr, uint32_t src_size, 286 uint64_t dst_addr, uint32_t *dst_size, 287 uint32_t data_size, uint8_t is_finalised, 288 uint32_t *mbox_error, uint32_t *send_id); 289 290 int intel_fcs_ecdsa_hash_sign_init(uint32_t session_id, uint32_t context_id, 291 uint32_t key_id, uint32_t param_size, 292 uint64_t param_data, uint32_t *mbox_error); 293 int intel_fcs_ecdsa_hash_sign_finalize(uint32_t smc_fid, uint32_t trans_id, 294 uint32_t session_id, uint32_t context_id, 295 uint32_t src_addr, uint32_t src_size, 296 uint64_t dst_addr, uint32_t *dst_size, 297 uint32_t *mbox_error); 298 299 int intel_fcs_ecdsa_hash_sig_verify_init(uint32_t session_id, uint32_t context_id, 300 uint32_t key_id, uint32_t param_size, 301 uint64_t param_data, uint32_t *mbox_error); 302 int intel_fcs_ecdsa_hash_sig_verify_finalize(uint32_t smc_fid, uint32_t trans_id, 303 uint32_t session_id, uint32_t context_id, 304 uint32_t src_addr, uint32_t src_size, 305 uint64_t dst_addr, uint32_t *dst_size, 306 uint32_t *mbox_error); 307 308 int intel_fcs_ecdsa_sha2_data_sign_init(uint32_t session_id, 309 uint32_t context_id, uint32_t key_id, 310 uint32_t param_size, uint64_t param_data, 311 uint32_t *mbox_error); 312 int intel_fcs_ecdsa_sha2_data_sign_update_finalize(uint32_t smc_fid, uint32_t trans_id, 313 uint32_t session_id, uint32_t context_id, 314 uint32_t src_addr, uint32_t src_size, 315 uint64_t dst_addr, uint32_t *dst_size, 316 uint8_t is_finalised, uint32_t *mbox_error, 317 uint64_t smmu_src_addr); 318 int intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(uint32_t session_id, 319 uint32_t context_id, uint32_t src_addr, 320 uint32_t src_size, uint64_t dst_addr, 321 uint32_t *dst_size, uint8_t is_finalised, 322 uint32_t *mbox_error, uint32_t *send_id); 323 324 int intel_fcs_ecdsa_sha2_data_sig_verify_init(uint32_t session_id, 325 uint32_t context_id, uint32_t key_id, 326 uint32_t param_size, uint64_t param_data, 327 uint32_t *mbox_error); 328 int intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(uint32_t smc_fid, uint32_t trans_id, 329 uint32_t session_id, uint32_t context_id, 330 uint32_t src_addr, uint32_t src_size, 331 uint64_t dst_addr, uint32_t *dst_size, 332 uint32_t data_size, uint8_t is_finalised, 333 uint32_t *mbox_error, uint64_t smmu_src_addr); 334 int intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(uint32_t session_id, 335 uint32_t context_id, uint32_t src_addr, 336 uint32_t src_size, uint64_t dst_addr, 337 uint32_t *dst_size, uint32_t data_size, 338 uint8_t is_finalised, uint32_t *mbox_error, 339 uint32_t *send_id); 340 341 int intel_fcs_ecdsa_get_pubkey_init(uint32_t session_id, uint32_t context_id, 342 uint32_t key_id, uint32_t param_size, 343 uint64_t param_data, uint32_t *mbox_error); 344 int intel_fcs_ecdsa_get_pubkey_finalize(uint32_t smc_fid, uint32_t trans_id, 345 uint32_t session_id, uint32_t context_id, 346 uint64_t dst_addr, uint32_t *dst_size, 347 uint32_t *mbox_error); 348 349 int intel_fcs_ecdh_request_init(uint32_t session_id, uint32_t context_id, 350 uint32_t key_id, uint32_t param_size, 351 uint64_t param_data, uint32_t *mbox_error); 352 int intel_fcs_ecdh_request_finalize(uint32_t smc_fid, uint32_t trans_id, 353 uint32_t session_id, uint32_t context_id, 354 uint32_t src_addr, uint32_t src_size, 355 uint64_t dst_addr, uint32_t *dst_size, 356 uint32_t *mbox_error); 357 358 int intel_fcs_aes_crypt_init(uint32_t session_id, uint32_t context_id, 359 uint32_t key_id, uint64_t param_addr, 360 uint32_t param_size, uint32_t *mbox_error); 361 int intel_fcs_aes_crypt_update_finalize(uint32_t smc_fid, uint32_t trans_id, 362 uint32_t session_id, uint32_t context_id, 363 uint64_t src_addr, uint32_t src_size, 364 uint64_t dst_addr, uint32_t dst_size, 365 uint32_t aad_size, uint8_t is_finalised, 366 uint32_t *send_id, uint64_t smmu_src_addr, 367 uint64_t smmu_dst_addr); 368 369 int intel_fcs_hkdf_request(uint32_t smc_fid, uint32_t trans_id, 370 uint32_t session_id, uint32_t step_type, 371 uint32_t mac_mode, uint32_t src_addr, 372 uint32_t key_uid, uint32_t op_key_size); 373 #endif /* SOCFPGA_FCS_H */ 374