1/* 2 * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <common/debug.h> 10#include <dsu_macros.S> 11#include <neoverse_e1.h> 12#include <cpu_macros.S> 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25workaround_reset_start neoverse_e1, ERRATUM(936184), ERRATA_DSU_936184 26 errata_dsu_936184_wa_impl 27workaround_reset_end neoverse_e1, ERRATUM(936184) 28 29check_erratum_custom_start neoverse_e1, ERRATUM(936184) 30 branch_if_scu_not_present 2f /* label 1 is used in the macro */ 31 check_errata_dsu_936184_impl 32 2: 33 ret 34check_erratum_custom_end neoverse_e1, ERRATUM(936184) 35 36cpu_reset_func_start neoverse_e1 37cpu_reset_func_end neoverse_e1 38 39func neoverse_e1_cpu_pwr_dwn 40 mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1 41 orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 42 msr NEOVERSE_E1_CPUPWRCTLR_EL1, x0 43 isb 44 ret 45endfunc neoverse_e1_cpu_pwr_dwn 46 47.section .rodata.neoverse_e1_regs, "aS" 48neoverse_e1_regs: /* The ascii list of register names to be reported */ 49 .asciz "cpuectlr_el1", "" 50 51func neoverse_e1_cpu_reg_dump 52 adr x6, neoverse_e1_regs 53 mrs x8, NEOVERSE_E1_ECTLR_EL1 54 ret 55endfunc neoverse_e1_cpu_reg_dump 56 57declare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \ 58 neoverse_e1_reset_func, \ 59 neoverse_e1_cpu_pwr_dwn 60