1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a715.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_cortex_a715_3699560 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31workaround_reset_start cortex_a715, ERRATUM(2331818), ERRATA_A715_2331818 32 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20) 33workaround_reset_end cortex_a715, ERRATUM(2331818) 34 35check_erratum_ls cortex_a715, ERRATUM(2331818), CPU_REV(1, 0) 36 37workaround_reset_start cortex_a715, ERRATUM(2344187), ERRATA_A715_2344187 38 /* GCR_EL1 is only present with FEAT_MTE2. */ 39 mrs x1, ID_AA64PFR1_EL1 40 ubfx x0, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4 41 cmp x0, #MTE_IMPLEMENTED_ELX 42 bne #1f 43 sysreg_bit_set GCR_EL1, GCR_EL1_RRND_BIT 44 451: 46 /* Mitigation upon ERETAA and ERETAB. */ 47 mov x0, #2 48 msr CORTEX_A715_CPUPSELR_EL3, x0 49 isb 50 ldr x0, =0xd69f0bff 51 msr CORTEX_A715_CPUPOR_EL3, x0 52 ldr x0, =0xfffffbff 53 msr CORTEX_A715_CPUPMR_EL3, x0 54 mov x1, #0 55 orr x1, x1, #(1<<0) 56 orr x1, x1, #(3<<4) 57 orr x1, x1, #(0xf<<6) 58 orr x1, x1, #(1<<13) 59 orr x1, x1, #(1<<53) 60 msr CORTEX_A715_CPUPCR_EL3, x1 61workaround_reset_end cortex_a715, ERRATUM(2344187) 62 63check_erratum_ls cortex_a715, ERRATUM(2344187), CPU_REV(1, 0) 64 65workaround_reset_start cortex_a715, ERRATUM(2413290), ERRATA_A715_2413290 66/* Erratum 2413290 workaround is required only if SPE is enabled */ 67#if ENABLE_SPE_FOR_NS != 0 68 /* Check if Static profiling extension is implemented or present. */ 69 mrs x1, id_aa64dfr0_el1 70 ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4 71 cbz x0, 1f 72 /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */ 73 sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(57) 74 sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(58) 751: 76#endif 77workaround_reset_end cortex_a715, ERRATUM(2413290) 78 79check_erratum_range cortex_a715, ERRATUM(2413290), CPU_REV(1,0), CPU_REV(1, 0) 80 81workaround_reset_start cortex_a715, ERRATUM(2420947), ERRATA_A715_2420947 82 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(33) 83workaround_reset_end cortex_a715, ERRATUM(2420947) 84 85check_erratum_range cortex_a715, ERRATUM(2420947), CPU_REV(1, 0), CPU_REV(1, 0) 86 87workaround_reset_start cortex_a715, ERRATUM(2429384), ERRATA_A715_2429384 88 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(27) 89workaround_reset_end cortex_a715, ERRATUM(2429384) 90 91check_erratum_range cortex_a715, ERRATUM(2429384), CPU_REV(1, 0), CPU_REV(1, 0) 92 93workaround_reset_start cortex_a715, ERRATUM(2561034), ERRATA_A715_2561034 94 sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(26) 95workaround_reset_end cortex_a715, ERRATUM(2561034) 96 97check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0) 98 99workaround_reset_start cortex_a715, ERRATUM(2728106), ERRATA_A715_2728106 100 mov x0, #3 101 msr CORTEX_A715_CPUPSELR_EL3, x0 102 isb 103 ldr x0, =0xd503339f 104 msr CORTEX_A715_CPUPOR_EL3, x0 105 ldr x0, =0xfffff3ff 106 msr CORTEX_A715_CPUPMR_EL3, x0 107 mov x0, #1 108 orr x0, x0, #(3<<4) 109 orr x0, x0, #(0xf<<6) 110 orr x0, x0, #(1<<13) 111 orr x0, x0, #(1<<20) 112 orr x0, x0, #(1<<22) 113 orr x0, x0, #(1<<31) 114 orr x0, x0, #(1<<50) 115 msr CORTEX_A715_CPUPCR_EL3, x0 116workaround_reset_end cortex_a715, ERRATUM(2728106) 117 118check_erratum_ls cortex_a715, ERRATUM(2728106), CPU_REV(1, 1) 119 120workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 121#if IMAGE_BL31 122 /* 123 * The Cortex-A715 generic vectors are overridden to apply errata 124 * mitigation on exception entry from lower ELs. 125 */ 126 override_vector_table wa_cve_vbar_cortex_a715 127#endif /* IMAGE_BL31 */ 128workaround_reset_end cortex_a715, CVE(2022, 23960) 129 130check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 131 132add_erratum_entry cortex_a715, ERRATUM(3699560), ERRATA_A715_3699560, NO_APPLY_AT_RESET 133 134check_erratum_ls cortex_a715, ERRATUM(3699560), CPU_REV(1, 3) 135 136cpu_reset_func_start cortex_a715 137 /* Disable speculative loads */ 138 msr SSBS, xzr 139cpu_reset_func_end cortex_a715 140 141 /* ---------------------------------------------------- 142 * HW will do the cache maintenance while powering down 143 * ---------------------------------------------------- 144 */ 145func cortex_a715_core_pwr_dwn 146 /* --------------------------------------------------- 147 * Enable CPU power down bit in power control register 148 * --------------------------------------------------- 149 */ 150 mrs x0, CORTEX_A715_CPUPWRCTLR_EL1 151 orr x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 152 msr CORTEX_A715_CPUPWRCTLR_EL1, x0 153 isb 154 ret 155endfunc cortex_a715_core_pwr_dwn 156 157 /* --------------------------------------------- 158 * This function provides Cortex-A715 specific 159 * register information for crash reporting. 160 * It needs to return with x6 pointing to 161 * a list of register names in ascii and 162 * x8 - x15 having values of registers to be 163 * reported. 164 * --------------------------------------------- 165 */ 166.section .rodata.cortex_a715_regs, "aS" 167cortex_a715_regs: /* The ascii list of register names to be reported */ 168 .asciz "cpuectlr_el1", "" 169 170func cortex_a715_cpu_reg_dump 171 adr x6, cortex_a715_regs 172 mrs x8, CORTEX_A715_CPUECTLR_EL1 173 ret 174endfunc cortex_a715_cpu_reg_dump 175 176declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \ 177 cortex_a715_reset_func, \ 178 cortex_a715_core_pwr_dwn 179