1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_TRACE_H 8 #define MT_SPM_TRACE_H 9 10 #include <lib/mmio.h> 11 #include <platform_def.h> 12 13 enum mt_spm_sysram_type { 14 MT_SPM_SYSRAM_COMMON, 15 MT_SPM_SYSRAM_SUSPEND, 16 MT_SPM_SYSRAM_LP, 17 }; 18 19 /* SPM trace common type */ 20 enum mt_spm_trace_common_type { 21 MT_SPM_TRACE_COMM_HAED, 22 MT_SPM_TRACE_COMM_FP, 23 MT_SPM_TRACE_COMM_RC_LAST_TIME_H, 24 MT_SPM_TRACE_COMM_RC_LAST_TIME_L, 25 MT_SPM_TRACE_COMM_RC_INFO, 26 MT_SPM_TRACE_COMM_RC_FP, 27 MT_SPM_TRACE_COMM_RC_VALID, 28 }; 29 30 /* SPM trace suspend type */ 31 enum mt_spm_trace_suspend_type { 32 MT_SPM_TRACE_SUSPEND_WAKE_SRC, 33 }; 34 35 /* 36 * SPM sram usage with mcdi sram 37 * start offset : 0x500 38 */ 39 #define MT_SPM_SYSRAM_BASE (MTK_LPM_SRAM_BASE + 0x500) 40 #define MT_SPM_SYSRAM_COMM_BASE MT_SPM_SYSRAM_BASE 41 #define MT_SPM_SYSRAM_COMM_SZ 0x20 42 43 #define MT_SPM_SYSRAM_SUSPEND_BASE \ 44 (MT_SPM_SYSRAM_BASE + MT_SPM_SYSRAM_COMM_SZ) 45 #define MT_SPM_SYSRAM_SUSPEND_SZ 0xe0 46 47 #define MT_SPM_SYSRAM_LP_BASE \ 48 (MT_SPM_SYSRAM_SUSPEND_BASE + MT_SPM_SYSRAM_SUSPEND_SZ) 49 50 #define MT_SPM_SYSRAM_SLOT(slot) ((slot) << 2u) 51 52 #ifndef MTK_PLAT_SPM_TRACE_UNSUPPORT 53 54 #define MT_SPM_SYSRAM_W(_s, type, val, _sz) \ 55 mt_spm_sysram_write(_s, type, val, _sz) 56 57 #define MT_SPM_SYSRAM_R_U32(addr, val) ({ \ 58 unsigned int *r_val = (unsigned int *)val; \ 59 if (r_val) \ 60 *r_val = mmio_read_32(addr); }) 61 62 #define MT_SPM_SYSRAM_R(_s, type, val) \ 63 mt_spm_sysram_read(_s, type, val) 64 65 /* SPM trace common */ 66 #define MT_SPM_TRACE_INIT(_magic) ({ \ 67 mt_spm_sysram_init(_magic); }) 68 69 #define MT_SPM_TRACE_COMMON_U32_WR(_type, _val) ({ \ 70 mmio_write_32((MT_SPM_SYSRAM_COMM_BASE + \ 71 MT_SPM_SYSRAM_SLOT(_type)), _val); }) 72 73 #define MT_SPM_TRACE_COMMON_WR(_type, val, _sz) ({ \ 74 int ret = MT_SPM_SYSRAM_W(MT_SPM_SYSRAM_COMMON, \ 75 _type, val, _sz); ret; }) 76 77 #define MT_SPM_TRACE_COMMON_U32_RD(_type, _val) ({ \ 78 MT_SPM_SYSRAM_R_U32((MT_SPM_SYSRAM_COMM_BASE + \ 79 MT_SPM_SYSRAM_SLOT(_type)), _val); }) 80 81 #define MT_SPM_TRACE_COMMON_RD(_type, _val) ({ \ 82 int ret = MT_SPM_SYSRAM_R(MT_SPM_SYSRAM_COMMON, \ 83 _type, _val); ret; }) 84 85 /* SPM trace suspend */ 86 #define MT_SPM_TRACE_SUSPEND_U32_WR(_type, _val) ({ \ 87 mmio_write_32((MT_SPM_SYSRAM_SUSPEND_BASE + \ 88 MT_SPM_SYSRAM_SLOT(_type)), _val); }) 89 90 #define MT_SPM_TRACE_SUSPEND_WR(_type, _val, _sz) ({ \ 91 int ret = MT_SPM_SYSRAM_W(MT_SPM_SYSRAM_SUSPEND, \ 92 _type, _val, _sz); ret; }) 93 94 #define MT_SPM_TRACE_SUSPEND_U32_RD(_type, _val) ({\ 95 MT_SPM_SYSRAM_R_U32((MT_SPM_SYSRAM_SUSPEND_BASE + \ 96 MT_SPM_SYSRAM_SLOT(_type)), _val); }) 97 98 #define MT_SPM_TRACE_SUSPEND_RD(_type, _val) ({ \ 99 int ret = MT_SPM_SYSRAM_R(MT_SPM_SYSRAM_SUSPEND, \ 100 _type, _val); ret; }) 101 102 /* SPM trace low power */ 103 #define MT_SPM_TRACE_LP_U32_WR(_type, _val) ({ \ 104 mmio_write_32((MT_SPM_SYSRAM_LP_BASE + \ 105 MT_SPM_SYSRAM_SLOT(_type)), _val); }) 106 107 #define MT_SPM_TRACE_LP_WR(_type, _val, _sz) ({ \ 108 int ret = MT_SPM_SYSRAM_W(MT_SPM_SYSRAM_LP, \ 109 _type, _val, _sz); ret; }) 110 111 #define MT_SPM_TRACE_LP_U32_RD(_type, _val) ({ \ 112 MT_SPM_SYSRAM_R_U32((MT_SPM_SYSRAM_LP_BASE + \ 113 MT_SPM_SYSRAM_SLOT(_type)), _val); }) 114 115 #define MT_SPM_TRACE_LP_RD(_type, _val) ({ \ 116 int ret = MT_SPM_SYSRAM_R(MT_SPM_SYSRAM_LP, \ 117 _type, _val); ret; }) 118 119 #define MT_SPM_TRACE_LP_RINGBUF(_pval, _sz) ({ \ 120 int ret = mt_spm_sysram_lp_ringbuf_add(_pval, _sz); ret; }) 121 122 int mt_spm_sysram_lp_ringbuf_add(const void *val, unsigned int sz); 123 124 int mt_spm_sysram_write(int section, int type, const void *val, 125 unsigned int sz); 126 int mt_spm_sysram_read(int section, int type, void *val); 127 128 int mt_spm_sysram_init(unsigned int magic); 129 #else 130 /* SPM trace common */ 131 #define MT_SPM_TRACE_INIT(_magic) 132 #define MT_SPM_TRACE_COMMON_U32_WR(type, val) 133 #define MT_SPM_TRACE_COMMON_WR(val) 134 #define MT_SPM_TRACE_COMMON_U32_RD(type, val) 135 #define MT_SPM_TRACE_COMMON_RD(val) 136 137 /* SPM trace suspend */ 138 #define MT_SPM_TRACE_SUSPEND_U32_WR(type, val) 139 #define MT_SPM_TRACE_SUSPEND_WR(val) 140 #define MT_SPM_TRACE_SUSPEND_U32_RD(type, val) 141 #define MT_SPM_TRACE_SUSPEND_RD(val) 142 143 /* SPM trace low power */ 144 #define MT_SPM_TRACE_LP_U32_WR(type, val) 145 #define MT_SPM_TRACE_LP_WR(val) 146 #define MT_SPM_TRACE_LP_U32_RD(type, val) 147 #define MT_SPM_TRACE_LP_RD(val) 148 #define MT_SPM_TRACE_LP_RINGBUF(pval, sz) 149 150 #define mt_spm_sysram_lp_ringbuf_add(_val, _sz) 151 #define mt_spm_sysram_write(_s, _type, _val, _sz) 152 #define mt_spm_sysram_read(_s, _type, _val) 153 #define mt_spm_sysram_init(_magic) 154 #endif 155 156 #endif /* MT_SPM_TRACE_H */ 157 158