1/* 2 * Copyright (c) 2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <caddo.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Caddo must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Caddo supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24#if ERRATA_SME_POWER_DOWN == 0 25#error "Caddo needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 26#endif 27 28cpu_reset_prologue caddo 29 30cpu_reset_func_start caddo 31 /* ---------------------------------------------------- 32 * Disable speculative loads 33 * ---------------------------------------------------- 34 */ 35 msr SSBS, xzr 36 enable_mpmm 37cpu_reset_func_end caddo 38 39func caddo_core_pwr_dwn 40 /* --------------------------------------------------- 41 * Flip CPU power down bit in power control register. 42 * It will be set on powerdown and cleared on wakeup 43 * --------------------------------------------------- 44 */ 45 sysreg_bit_toggle CADDO_IMP_CPUPWRCTLR_EL1, \ 46 CADDO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 47 isb 48 signal_pabandon_handled 49 ret 50endfunc caddo_core_pwr_dwn 51 52.section .rodata.caddo_regs, "aS" 53caddo_regs: /* The ASCII list of register names to be reported */ 54 .asciz "cpuectlr_el1", "" 55 56func caddo_cpu_reg_dump 57 adr x6, caddo_regs 58 mrs x8, CADDO_IMP_CPUECTLR_EL1 59 ret 60endfunc caddo_cpu_reg_dump 61 62declare_cpu_ops caddo, CADDO_MIDR, \ 63 caddo_reset_func, \ 64 caddo_core_pwr_dwn 65