feat(marvell): add trng driver

Armada-7K/8K and CN913x integrated the Rambus EIP-97 IP on CP11x die. It
supports to generate up to 4 32-bit random number in one shot.

This trivial driver provisions

feat(marvell): add trng driver

Armada-7K/8K and CN913x integrated the Rambus EIP-97 IP on CP11x die. It
supports to generate up to 4 32-bit random number in one shot.

This trivial driver provisions a simple API to read the random numbers
from hardware. It allows the bootloader to get one 32-bit or 64-bit
random number via SMC call to support KASLR.

Change-Id: I1707a85512ca163b8c7ab1644ff0f7e2fcf57344
Signed-off-by: Wilson Ding <dingwei@marvell.com>

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fix(plat/marvell/a3720/uart): do external reset during initialization

Sometimes when changing UART clock from TBG to XTAL, UART HW enters into
some broken state. It does not transit characters from

fix(plat/marvell/a3720/uart): do external reset during initialization

Sometimes when changing UART clock from TBG to XTAL, UART HW enters into
some broken state. It does not transit characters from TX FIFO anymore
and TX FIFO stays always empty. TX FIFO reset does not recover UART HW
from this broken state.

Experiments show that external reset can fix UART HW from this broken
state.

TF-A fatal error handler calls console_a3700_core_init() function to
initialize UART HW. This handler may be called anytime during CPU
runtime, also when kernel is running.

U-Boot or Linux kernel may change UART clock to TBG to achieve higher
baudrates. During initialization, console_a3700_core_init() resets UART
configuration to default settings, which means that it also changes
UART clock from TBG to XTAL.

Do an external reset of UART via North Bridge Peripheral reset register
to prevent this UART hangup.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8990bce24d1a6fd8ccc47a2cd0a5ff932fcfcf14

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