xref: /rk3399_ARM-atf/plat/arm/board/a5ds/aarch32/a5ds_helpers.S (revision d5dfdeb65ff5b7f24dded201d2945c7b74565ce8)
1/*
2 * Copyright (c) 2019, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <platform_def.h>
10
11	.globl	plat_secondary_cold_boot_setup
12	.globl	plat_get_my_entrypoint
13	.globl	plat_is_my_cpu_primary
14
15	/* --------------------------------------------------------------------
16	 * void plat_secondary_cold_boot_setup (void);
17	 *
18	 * For AArch32, cold-booting secondary CPUs is not yet
19	 * implemented and they panic.
20	 * --------------------------------------------------------------------
21	 */
22func plat_secondary_cold_boot_setup
23cb_panic:
24	wfi
25	b	cb_panic
26endfunc plat_secondary_cold_boot_setup
27
28	/* ---------------------------------------------------------------------
29	 * unsigned long plat_get_my_entrypoint (void);
30	 *
31	 * Main job of this routine is to distinguish between a cold and warm
32	 * boot.
33	 * ---------------------------------------------------------------------
34	 */
35func plat_get_my_entrypoint
36	/* TODO support warm boot */
37	/* Cold reset */
38	mov	r0, #0
39	bx	lr
40
41endfunc plat_get_my_entrypoint
42
43	/* -----------------------------------------------------
44	 * unsigned int plat_is_my_cpu_primary (void);
45	 *
46	 * Find out whether the current cpu is the primary
47	 * cpu.
48	 * -----------------------------------------------------
49	 */
50func plat_is_my_cpu_primary
51	ldcopr	r0, MPIDR
52	ldr	r1, =MPIDR_AFFINITY_MASK
53	and	r0, r1
54	cmp	r0, #0
55	moveq	r0, #1
56	movne	r0, #0
57	bx	lr
58endfunc plat_is_my_cpu_primary
59