1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #ifndef MARVELL_DEF_H 9 #define MARVELL_DEF_H 10 11 #include <platform_def.h> 12 13 #include <arch.h> 14 #include <common/tbbr/tbbr_img_def.h> 15 #include <lib/xlat_tables/xlat_tables_v2.h> 16 #include <plat/common/common_def.h> 17 18 /****************************************************************************** 19 * Definitions common to all MARVELL standard platforms 20 *****************************************************************************/ 21 22 /* Special value used to verify platform parameters from BL2 to BL31 */ 23 #define MARVELL_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 24 25 26 #define MARVELL_CACHE_WRITEBACK_SHIFT 6 27 28 /* 29 * Macros mapping the MPIDR Affinity levels to MARVELL Platform Power levels. 30 * The power levels have a 1:1 mapping with the MPIDR affinity levels. 31 */ 32 #define MARVELL_PWR_LVL0 MPIDR_AFFLVL0 33 #define MARVELL_PWR_LVL1 MPIDR_AFFLVL1 34 #define MARVELL_PWR_LVL2 MPIDR_AFFLVL2 35 36 /* 37 * Macros for local power states in Marvell platforms encoded by 38 * State-ID field within the power-state parameter. 39 */ 40 /* Local power state for power domains in Run state. */ 41 #define MARVELL_LOCAL_STATE_RUN 0 42 /* Local power state for retention. Valid only for CPU power domains */ 43 #define MARVELL_LOCAL_STATE_RET 1 44 /* 45 * Local power state for OFF/power-down. Valid for CPU 46 * and cluster power domains 47 */ 48 #define MARVELL_LOCAL_STATE_OFF 2 49 50 /* This leaves a gap between end of DRAM and start of ROM block */ 51 #define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */ 52 53 /* The first 4KB of Trusted SRAM are used as shared memory */ 54 #define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE 55 #define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ 56 57 /* The remaining Trusted SRAM is used to load the BL images */ 58 #define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \ 59 MARVELL_SHARED_RAM_SIZE) 60 #define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \ 61 MARVELL_SHARED_RAM_SIZE) 62 /* Non-shared DRAM */ 63 #define MARVELL_DRAM_BASE ULL(0x0) 64 #define MARVELL_DRAM_SIZE ULL(0x80000000) 65 #define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \ 66 MARVELL_DRAM_SIZE - 1) 67 68 #define MARVELL_IRQ_PIC0 28 69 #define MARVELL_IRQ_SEC_PHY_TIMER 29 70 71 #define MARVELL_IRQ_SEC_SGI_0 8 72 #define MARVELL_IRQ_SEC_SGI_1 9 73 #define MARVELL_IRQ_SEC_SGI_2 10 74 #define MARVELL_IRQ_SEC_SGI_3 11 75 #define MARVELL_IRQ_SEC_SGI_4 12 76 #define MARVELL_IRQ_SEC_SGI_5 13 77 #define MARVELL_IRQ_SEC_SGI_6 14 78 #define MARVELL_IRQ_SEC_SGI_7 15 79 80 #if LLC_SRAM 81 /* The entire LLC SRAM should be marked as secure in MMU tables, 82 * otherwise any access to it will produce exception 83 */ 84 #define MARVELL_MAP_SECURE_RAM MAP_REGION_FLAT( \ 85 PLAT_MARVELL_LLC_SRAM_BASE,\ 86 PLAT_MARVELL_LLC_SRAM_SIZE,\ 87 MT_MEMORY | MT_RW | MT_SECURE) 88 #else 89 #define MARVELL_MAP_SECURE_RAM MAP_REGION_FLAT( \ 90 MARVELL_SHARED_RAM_BASE, \ 91 MARVELL_SHARED_RAM_SIZE, \ 92 MT_MEMORY | MT_RW | MT_SECURE) 93 #endif 94 #define MARVELL_MAP_DRAM MAP_REGION_FLAT( \ 95 MARVELL_DRAM_BASE, \ 96 MARVELL_DRAM_SIZE, \ 97 MT_MEMORY | MT_RW | MT_NS) 98 99 /* 100 * The number of regions like RO(code), coherent and data required by 101 * different BL stages which need to be mapped in the MMU. 102 */ 103 #if USE_COHERENT_MEM 104 #define MARVELL_BL_REGIONS 3 105 #else 106 #define MARVELL_BL_REGIONS 2 107 #endif 108 109 #define MAX_MMAP_REGIONS (PLAT_MARVELL_MMAP_ENTRIES + \ 110 MARVELL_BL_REGIONS) 111 112 #define MARVELL_CONSOLE_BAUDRATE 115200 113 114 /****************************************************************************** 115 * Required platform porting definitions common to all MARVELL std. platforms 116 *****************************************************************************/ 117 118 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 119 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 120 121 /* 122 * This macro defines the deepest retention state possible. A higher state 123 * id will represent an invalid or a power down state. 124 */ 125 #define PLAT_MAX_RET_STATE MARVELL_LOCAL_STATE_RET 126 127 /* 128 * This macro defines the deepest power down states possible. Any state ID 129 * higher than this is invalid. 130 */ 131 #define PLAT_MAX_OFF_STATE MARVELL_LOCAL_STATE_OFF 132 133 134 #define PLATFORM_CORE_COUNT PLAT_MARVELL_CORE_COUNT 135 #define PLAT_NUM_PWR_DOMAINS (PLAT_MARVELL_CLUSTER_COUNT + \ 136 PLATFORM_CORE_COUNT) 137 138 /* 139 * Some data must be aligned on the biggest cache line size in the platform. 140 * This is known only to the platform as it might have a combination of 141 * integrated and external caches. 142 */ 143 #define CACHE_WRITEBACK_GRANULE (1 << MARVELL_CACHE_WRITEBACK_SHIFT) 144 145 146 /******************************************************************************* 147 * BL1 specific defines. 148 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 149 * addresses. 150 ******************************************************************************/ 151 #define BL1_RO_BASE PLAT_MARVELL_TRUSTED_ROM_BASE 152 #define BL1_RO_LIMIT (PLAT_MARVELL_TRUSTED_ROM_BASE \ 153 + PLAT_MARVELL_TRUSTED_ROM_SIZE) 154 /* 155 * Put BL1 RW at the top of the Trusted SRAM. 156 */ 157 #define BL1_RW_BASE (MARVELL_BL_RAM_BASE + \ 158 MARVELL_BL_RAM_SIZE - \ 159 PLAT_MARVELL_MAX_BL1_RW_SIZE) 160 #define BL1_RW_LIMIT (MARVELL_BL_RAM_BASE + MARVELL_BL_RAM_SIZE) 161 162 /******************************************************************************* 163 * BLE specific defines. 164 ******************************************************************************/ 165 #define BLE_BASE PLAT_MARVELL_SRAM_BASE 166 #define BLE_LIMIT PLAT_MARVELL_SRAM_END 167 168 /******************************************************************************* 169 * BL2 specific defines. 170 ******************************************************************************/ 171 /* 172 * Put BL2 just below BL31. 173 */ 174 #define BL2_BASE (BL31_BASE - PLAT_MARVELL_MAX_BL2_SIZE) 175 #define BL2_LIMIT BL31_BASE 176 177 /******************************************************************************* 178 * BL31 specific defines. 179 ******************************************************************************/ 180 /* 181 * Put BL31 at the top of the Trusted SRAM. 182 */ 183 #define BL31_BASE (MARVELL_BL_RAM_BASE + \ 184 MARVELL_BL_RAM_SIZE - \ 185 PLAT_MARVEL_MAX_BL31_SIZE) 186 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 187 #define BL31_LIMIT (MARVELL_BL_RAM_BASE + \ 188 MARVELL_BL_RAM_SIZE) 189 190 /******************************************************************************* 191 * BL32 specific defines. 192 ******************************************************************************/ 193 #define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE 194 #define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE) 195 196 #ifdef SPD_none 197 #undef BL32_BASE 198 #endif /* SPD_none */ 199 200 #endif /* MARVELL_DEF_H */ 201