1 /* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_H 8 #define ARCH_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * MIDR bit definitions 14 ******************************************************************************/ 15 #define MIDR_IMPL_MASK U(0xff) 16 #define MIDR_IMPL_SHIFT U(24) 17 #define MIDR_VAR_SHIFT U(20) 18 #define MIDR_VAR_BITS U(4) 19 #define MIDR_REV_SHIFT U(0) 20 #define MIDR_REV_BITS U(4) 21 #define MIDR_PN_MASK U(0xfff) 22 #define MIDR_PN_SHIFT U(4) 23 24 /******************************************************************************* 25 * MPIDR macros 26 ******************************************************************************/ 27 #define MPIDR_MT_MASK (U(1) << 24) 28 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 29 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 30 #define MPIDR_AFFINITY_BITS U(8) 31 #define MPIDR_AFFLVL_MASK U(0xff) 32 #define MPIDR_AFFLVL_SHIFT U(3) 33 #define MPIDR_AFF0_SHIFT U(0) 34 #define MPIDR_AFF1_SHIFT U(8) 35 #define MPIDR_AFF2_SHIFT U(16) 36 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 37 #define MPIDR_AFFINITY_MASK U(0x00ffffff) 38 #define MPIDR_AFFLVL0 U(0) 39 #define MPIDR_AFFLVL1 U(1) 40 #define MPIDR_AFFLVL2 U(2) 41 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 42 43 #define MPIDR_AFFLVL0_VAL(mpidr) \ 44 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 45 #define MPIDR_AFFLVL1_VAL(mpidr) \ 46 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 47 #define MPIDR_AFFLVL2_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL3_VAL(mpidr) U(0) 50 51 #define MPIDR_AFF_ID(mpid, n) \ 52 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 53 54 #define MPID_MASK (MPIDR_MT_MASK |\ 55 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\ 56 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\ 57 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 58 59 /* 60 * An invalid MPID. This value can be used by functions that return an MPID to 61 * indicate an error. 62 */ 63 #define INVALID_MPID U(0xFFFFFFFF) 64 65 /* 66 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 67 * add one while using this macro to define array sizes. 68 */ 69 #define MPIDR_MAX_AFFLVL U(2) 70 71 /* Data Cache set/way op type defines */ 72 #define DC_OP_ISW U(0x0) 73 #define DC_OP_CISW U(0x1) 74 #if ERRATA_A53_827319 75 #define DC_OP_CSW DC_OP_CISW 76 #else 77 #define DC_OP_CSW U(0x2) 78 #endif 79 80 /******************************************************************************* 81 * Generic timer memory mapped registers & offsets 82 ******************************************************************************/ 83 #define CNTCR_OFF U(0x000) 84 /* Counter Count Value Lower register */ 85 #define CNTCVL_OFF U(0x008) 86 /* Counter Count Value Upper register */ 87 #define CNTCVU_OFF U(0x00C) 88 #define CNTFID_OFF U(0x020) 89 90 #define CNTCR_EN (U(1) << 0) 91 #define CNTCR_HDBG (U(1) << 1) 92 #define CNTCR_FCREQ(x) ((x) << 8) 93 94 /******************************************************************************* 95 * System register bit definitions 96 ******************************************************************************/ 97 /* CLIDR definitions */ 98 #define LOUIS_SHIFT U(21) 99 #define LOC_SHIFT U(24) 100 #define CLIDR_FIELD_WIDTH U(3) 101 102 /* CSSELR definitions */ 103 #define LEVEL_SHIFT U(1) 104 105 /* ID_MMFR4 definitions */ 106 #define ID_MMFR4_CNP_SHIFT U(12) 107 #define ID_MMFR4_CNP_LENGTH U(4) 108 #define ID_MMFR4_CNP_MASK U(0xf) 109 110 /* ID_PFR0 definitions */ 111 #define ID_PFR0_AMU_SHIFT U(20) 112 #define ID_PFR0_AMU_LENGTH U(4) 113 #define ID_PFR0_AMU_MASK U(0xf) 114 115 #define ID_PFR0_DIT_SHIFT U(24) 116 #define ID_PFR0_DIT_LENGTH U(4) 117 #define ID_PFR0_DIT_MASK U(0xf) 118 #define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT) 119 120 /* ID_PFR1 definitions */ 121 #define ID_PFR1_VIRTEXT_SHIFT U(12) 122 #define ID_PFR1_VIRTEXT_MASK U(0xf) 123 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 124 & ID_PFR1_VIRTEXT_MASK) 125 #define ID_PFR1_GENTIMER_SHIFT U(16) 126 #define ID_PFR1_GENTIMER_MASK U(0xf) 127 #define ID_PFR1_GIC_SHIFT U(28) 128 #define ID_PFR1_GIC_MASK U(0xf) 129 130 /* SCTLR definitions */ 131 #define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \ 132 (U(1) << 3)) 133 #if ARM_ARCH_MAJOR == 7 134 #define SCTLR_RES1 SCTLR_RES1_DEF 135 #else 136 #define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11)) 137 #endif 138 #define SCTLR_M_BIT (U(1) << 0) 139 #define SCTLR_A_BIT (U(1) << 1) 140 #define SCTLR_C_BIT (U(1) << 2) 141 #define SCTLR_CP15BEN_BIT (U(1) << 5) 142 #define SCTLR_ITD_BIT (U(1) << 7) 143 #define SCTLR_Z_BIT (U(1) << 11) 144 #define SCTLR_I_BIT (U(1) << 12) 145 #define SCTLR_V_BIT (U(1) << 13) 146 #define SCTLR_RR_BIT (U(1) << 14) 147 #define SCTLR_NTWI_BIT (U(1) << 16) 148 #define SCTLR_NTWE_BIT (U(1) << 18) 149 #define SCTLR_WXN_BIT (U(1) << 19) 150 #define SCTLR_UWXN_BIT (U(1) << 20) 151 #define SCTLR_EE_BIT (U(1) << 25) 152 #define SCTLR_TRE_BIT (U(1) << 28) 153 #define SCTLR_AFE_BIT (U(1) << 29) 154 #define SCTLR_TE_BIT (U(1) << 30) 155 #define SCTLR_DSSBS_BIT (U(1) << 31) 156 #define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \ 157 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT) 158 159 /* SDCR definitions */ 160 #define SDCR_SPD(x) ((x) << 14) 161 #define SDCR_SPD_LEGACY U(0x0) 162 #define SDCR_SPD_DISABLE U(0x2) 163 #define SDCR_SPD_ENABLE U(0x3) 164 #define SDCR_SCCD_BIT (U(1) << 23) 165 #define SDCR_RESET_VAL U(0x0) 166 167 /* HSCTLR definitions */ 168 #define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 169 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 170 (U(1) << 11) | (U(1) << 4) | (U(1) << 3)) 171 172 #define HSCTLR_M_BIT (U(1) << 0) 173 #define HSCTLR_A_BIT (U(1) << 1) 174 #define HSCTLR_C_BIT (U(1) << 2) 175 #define HSCTLR_CP15BEN_BIT (U(1) << 5) 176 #define HSCTLR_ITD_BIT (U(1) << 7) 177 #define HSCTLR_SED_BIT (U(1) << 8) 178 #define HSCTLR_I_BIT (U(1) << 12) 179 #define HSCTLR_WXN_BIT (U(1) << 19) 180 #define HSCTLR_EE_BIT (U(1) << 25) 181 #define HSCTLR_TE_BIT (U(1) << 30) 182 183 /* CPACR definitions */ 184 #define CPACR_FPEN(x) ((x) << 20) 185 #define CPACR_FP_TRAP_PL0 U(0x1) 186 #define CPACR_FP_TRAP_ALL U(0x2) 187 #define CPACR_FP_TRAP_NONE U(0x3) 188 189 /* SCR definitions */ 190 #define SCR_TWE_BIT (U(1) << 13) 191 #define SCR_TWI_BIT (U(1) << 12) 192 #define SCR_SIF_BIT (U(1) << 9) 193 #define SCR_HCE_BIT (U(1) << 8) 194 #define SCR_SCD_BIT (U(1) << 7) 195 #define SCR_NET_BIT (U(1) << 6) 196 #define SCR_AW_BIT (U(1) << 5) 197 #define SCR_FW_BIT (U(1) << 4) 198 #define SCR_EA_BIT (U(1) << 3) 199 #define SCR_FIQ_BIT (U(1) << 2) 200 #define SCR_IRQ_BIT (U(1) << 1) 201 #define SCR_NS_BIT (U(1) << 0) 202 #define SCR_VALID_BIT_MASK U(0x33ff) 203 #define SCR_RESET_VAL U(0x0) 204 205 #define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT) 206 207 /* HCR definitions */ 208 #define HCR_TGE_BIT (U(1) << 27) 209 #define HCR_AMO_BIT (U(1) << 5) 210 #define HCR_IMO_BIT (U(1) << 4) 211 #define HCR_FMO_BIT (U(1) << 3) 212 #define HCR_RESET_VAL U(0x0) 213 214 /* CNTHCTL definitions */ 215 #define CNTHCTL_RESET_VAL U(0x0) 216 #define PL1PCEN_BIT (U(1) << 1) 217 #define PL1PCTEN_BIT (U(1) << 0) 218 219 /* CNTKCTL definitions */ 220 #define PL0PTEN_BIT (U(1) << 9) 221 #define PL0VTEN_BIT (U(1) << 8) 222 #define PL0PCTEN_BIT (U(1) << 0) 223 #define PL0VCTEN_BIT (U(1) << 1) 224 #define EVNTEN_BIT (U(1) << 2) 225 #define EVNTDIR_BIT (U(1) << 3) 226 #define EVNTI_SHIFT U(4) 227 #define EVNTI_MASK U(0xf) 228 229 /* HCPTR definitions */ 230 #define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff)) 231 #define TCPAC_BIT (U(1) << 31) 232 #define TAM_BIT (U(1) << 30) 233 #define TTA_BIT (U(1) << 20) 234 #define TCP11_BIT (U(1) << 11) 235 #define TCP10_BIT (U(1) << 10) 236 #define HCPTR_RESET_VAL HCPTR_RES1 237 238 /* VTTBR defintions */ 239 #define VTTBR_RESET_VAL ULL(0x0) 240 #define VTTBR_VMID_MASK ULL(0xff) 241 #define VTTBR_VMID_SHIFT U(48) 242 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 243 #define VTTBR_BADDR_SHIFT U(0) 244 245 /* HDCR definitions */ 246 #define HDCR_RESET_VAL U(0x0) 247 248 /* HSTR definitions */ 249 #define HSTR_RESET_VAL U(0x0) 250 251 /* CNTHP_CTL definitions */ 252 #define CNTHP_CTL_RESET_VAL U(0x0) 253 254 /* NSACR definitions */ 255 #define NSASEDIS_BIT (U(1) << 15) 256 #define NSTRCDIS_BIT (U(1) << 20) 257 #define NSACR_CP11_BIT (U(1) << 11) 258 #define NSACR_CP10_BIT (U(1) << 10) 259 #define NSACR_IMP_DEF_MASK (U(0x7) << 16) 260 #define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT) 261 #define NSACR_RESET_VAL U(0x0) 262 263 /* CPACR definitions */ 264 #define ASEDIS_BIT (U(1) << 31) 265 #define TRCDIS_BIT (U(1) << 28) 266 #define CPACR_CP11_SHIFT U(22) 267 #define CPACR_CP10_SHIFT U(20) 268 #define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\ 269 (U(0x3) << CPACR_CP10_SHIFT)) 270 #define CPACR_RESET_VAL U(0x0) 271 272 /* FPEXC definitions */ 273 #define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8)) 274 #define FPEXC_EN_BIT (U(1) << 30) 275 #define FPEXC_RESET_VAL FPEXC_RES1 276 277 /* SPSR/CPSR definitions */ 278 #define SPSR_FIQ_BIT (U(1) << 0) 279 #define SPSR_IRQ_BIT (U(1) << 1) 280 #define SPSR_ABT_BIT (U(1) << 2) 281 #define SPSR_AIF_SHIFT U(6) 282 #define SPSR_AIF_MASK U(0x7) 283 284 #define SPSR_E_SHIFT U(9) 285 #define SPSR_E_MASK U(0x1) 286 #define SPSR_E_LITTLE U(0) 287 #define SPSR_E_BIG U(1) 288 289 #define SPSR_T_SHIFT U(5) 290 #define SPSR_T_MASK U(0x1) 291 #define SPSR_T_ARM U(0) 292 #define SPSR_T_THUMB U(1) 293 294 #define SPSR_MODE_SHIFT U(0) 295 #define SPSR_MODE_MASK U(0x7) 296 297 #define SPSR_SSBS_BIT BIT_32(23) 298 299 #define DISABLE_ALL_EXCEPTIONS \ 300 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT) 301 302 #define CPSR_DIT_BIT (U(1) << 21) 303 /* 304 * TTBCR definitions 305 */ 306 #define TTBCR_EAE_BIT (U(1) << 31) 307 308 #define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28) 309 #define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28) 310 #define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28) 311 312 #define TTBCR_RGN1_OUTER_NC (U(0x0) << 26) 313 #define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26) 314 #define TTBCR_RGN1_OUTER_WT (U(0x2) << 26) 315 #define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26) 316 317 #define TTBCR_RGN1_INNER_NC (U(0x0) << 24) 318 #define TTBCR_RGN1_INNER_WBA (U(0x1) << 24) 319 #define TTBCR_RGN1_INNER_WT (U(0x2) << 24) 320 #define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24) 321 322 #define TTBCR_EPD1_BIT (U(1) << 23) 323 #define TTBCR_A1_BIT (U(1) << 22) 324 325 #define TTBCR_T1SZ_SHIFT U(16) 326 #define TTBCR_T1SZ_MASK U(0x7) 327 #define TTBCR_TxSZ_MIN U(0) 328 #define TTBCR_TxSZ_MAX U(7) 329 330 #define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12) 331 #define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12) 332 #define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12) 333 334 #define TTBCR_RGN0_OUTER_NC (U(0x0) << 10) 335 #define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10) 336 #define TTBCR_RGN0_OUTER_WT (U(0x2) << 10) 337 #define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10) 338 339 #define TTBCR_RGN0_INNER_NC (U(0x0) << 8) 340 #define TTBCR_RGN0_INNER_WBA (U(0x1) << 8) 341 #define TTBCR_RGN0_INNER_WT (U(0x2) << 8) 342 #define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8) 343 344 #define TTBCR_EPD0_BIT (U(1) << 7) 345 #define TTBCR_T0SZ_SHIFT U(0) 346 #define TTBCR_T0SZ_MASK U(0x7) 347 348 /* 349 * HTCR definitions 350 */ 351 #define HTCR_RES1 ((U(1) << 31) | (U(1) << 23)) 352 353 #define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12) 354 #define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12) 355 #define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12) 356 357 #define HTCR_RGN0_OUTER_NC (U(0x0) << 10) 358 #define HTCR_RGN0_OUTER_WBA (U(0x1) << 10) 359 #define HTCR_RGN0_OUTER_WT (U(0x2) << 10) 360 #define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10) 361 362 #define HTCR_RGN0_INNER_NC (U(0x0) << 8) 363 #define HTCR_RGN0_INNER_WBA (U(0x1) << 8) 364 #define HTCR_RGN0_INNER_WT (U(0x2) << 8) 365 #define HTCR_RGN0_INNER_WBNA (U(0x3) << 8) 366 367 #define HTCR_T0SZ_SHIFT U(0) 368 #define HTCR_T0SZ_MASK U(0x7) 369 370 #define MODE_RW_SHIFT U(0x4) 371 #define MODE_RW_MASK U(0x1) 372 #define MODE_RW_32 U(0x1) 373 374 #define MODE32_SHIFT U(0) 375 #define MODE32_MASK U(0x1f) 376 #define MODE32_usr U(0x10) 377 #define MODE32_fiq U(0x11) 378 #define MODE32_irq U(0x12) 379 #define MODE32_svc U(0x13) 380 #define MODE32_mon U(0x16) 381 #define MODE32_abt U(0x17) 382 #define MODE32_hyp U(0x1a) 383 #define MODE32_und U(0x1b) 384 #define MODE32_sys U(0x1f) 385 386 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 387 388 #define SPSR_MODE32(mode, isa, endian, aif) \ 389 ((MODE_RW_32 << MODE_RW_SHIFT | \ 390 ((mode) & MODE32_MASK) << MODE32_SHIFT | \ 391 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ 392 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ 393 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) & \ 394 (~(SPSR_SSBS_BIT))) 395 396 /* 397 * TTBR definitions 398 */ 399 #define TTBR_CNP_BIT ULL(0x1) 400 401 /* 402 * CTR definitions 403 */ 404 #define CTR_CWG_SHIFT U(24) 405 #define CTR_CWG_MASK U(0xf) 406 #define CTR_ERG_SHIFT U(20) 407 #define CTR_ERG_MASK U(0xf) 408 #define CTR_DMINLINE_SHIFT U(16) 409 #define CTR_DMINLINE_WIDTH U(4) 410 #define CTR_DMINLINE_MASK ((U(1) << 4) - U(1)) 411 #define CTR_L1IP_SHIFT U(14) 412 #define CTR_L1IP_MASK U(0x3) 413 #define CTR_IMINLINE_SHIFT U(0) 414 #define CTR_IMINLINE_MASK U(0xf) 415 416 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 417 418 /* PMCR definitions */ 419 #define PMCR_N_SHIFT U(11) 420 #define PMCR_N_MASK U(0x1f) 421 #define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT) 422 #define PMCR_LC_BIT (U(1) << 6) 423 #define PMCR_DP_BIT (U(1) << 5) 424 425 /******************************************************************************* 426 * Definitions of register offsets, fields and macros for CPU system 427 * instructions. 428 ******************************************************************************/ 429 430 #define TLBI_ADDR_SHIFT U(0) 431 #define TLBI_ADDR_MASK U(0xFFFFF000) 432 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 433 434 /******************************************************************************* 435 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 436 * system level implementation of the Generic Timer. 437 ******************************************************************************/ 438 #define CNTCTLBASE_CNTFRQ U(0x0) 439 #define CNTNSAR U(0x4) 440 #define CNTNSAR_NS_SHIFT(x) (x) 441 442 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 443 #define CNTACR_RPCT_SHIFT U(0x0) 444 #define CNTACR_RVCT_SHIFT U(0x1) 445 #define CNTACR_RFRQ_SHIFT U(0x2) 446 #define CNTACR_RVOFF_SHIFT U(0x3) 447 #define CNTACR_RWVT_SHIFT U(0x4) 448 #define CNTACR_RWPT_SHIFT U(0x5) 449 450 /******************************************************************************* 451 * Definitions of register offsets and fields in the CNTBaseN Frame of the 452 * system level implementation of the Generic Timer. 453 ******************************************************************************/ 454 /* Physical Count register. */ 455 #define CNTPCT_LO U(0x0) 456 /* Counter Frequency register. */ 457 #define CNTBASEN_CNTFRQ U(0x10) 458 /* Physical Timer CompareValue register. */ 459 #define CNTP_CVAL_LO U(0x20) 460 /* Physical Timer Control register. */ 461 #define CNTP_CTL U(0x2c) 462 463 /* Physical timer control register bit fields shifts and masks */ 464 #define CNTP_CTL_ENABLE_SHIFT 0 465 #define CNTP_CTL_IMASK_SHIFT 1 466 #define CNTP_CTL_ISTATUS_SHIFT 2 467 468 #define CNTP_CTL_ENABLE_MASK U(1) 469 #define CNTP_CTL_IMASK_MASK U(1) 470 #define CNTP_CTL_ISTATUS_MASK U(1) 471 472 /* MAIR macros */ 473 #define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3))) 474 #define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3))) 475 476 /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */ 477 #define SCR p15, 0, c1, c1, 0 478 #define SCTLR p15, 0, c1, c0, 0 479 #define ACTLR p15, 0, c1, c0, 1 480 #define SDCR p15, 0, c1, c3, 1 481 #define MPIDR p15, 0, c0, c0, 5 482 #define MIDR p15, 0, c0, c0, 0 483 #define HVBAR p15, 4, c12, c0, 0 484 #define VBAR p15, 0, c12, c0, 0 485 #define MVBAR p15, 0, c12, c0, 1 486 #define NSACR p15, 0, c1, c1, 2 487 #define CPACR p15, 0, c1, c0, 2 488 #define DCCIMVAC p15, 0, c7, c14, 1 489 #define DCCMVAC p15, 0, c7, c10, 1 490 #define DCIMVAC p15, 0, c7, c6, 1 491 #define DCCISW p15, 0, c7, c14, 2 492 #define DCCSW p15, 0, c7, c10, 2 493 #define DCISW p15, 0, c7, c6, 2 494 #define CTR p15, 0, c0, c0, 1 495 #define CNTFRQ p15, 0, c14, c0, 0 496 #define ID_MMFR4 p15, 0, c0, c2, 6 497 #define ID_PFR0 p15, 0, c0, c1, 0 498 #define ID_PFR1 p15, 0, c0, c1, 1 499 #define MAIR0 p15, 0, c10, c2, 0 500 #define MAIR1 p15, 0, c10, c2, 1 501 #define TTBCR p15, 0, c2, c0, 2 502 #define TTBR0 p15, 0, c2, c0, 0 503 #define TTBR1 p15, 0, c2, c0, 1 504 #define TLBIALL p15, 0, c8, c7, 0 505 #define TLBIALLH p15, 4, c8, c7, 0 506 #define TLBIALLIS p15, 0, c8, c3, 0 507 #define TLBIMVA p15, 0, c8, c7, 1 508 #define TLBIMVAA p15, 0, c8, c7, 3 509 #define TLBIMVAAIS p15, 0, c8, c3, 3 510 #define TLBIMVAHIS p15, 4, c8, c3, 1 511 #define BPIALLIS p15, 0, c7, c1, 6 512 #define BPIALL p15, 0, c7, c5, 6 513 #define ICIALLU p15, 0, c7, c5, 0 514 #define HSCTLR p15, 4, c1, c0, 0 515 #define HCR p15, 4, c1, c1, 0 516 #define HCPTR p15, 4, c1, c1, 2 517 #define HSTR p15, 4, c1, c1, 3 518 #define CNTHCTL p15, 4, c14, c1, 0 519 #define CNTKCTL p15, 0, c14, c1, 0 520 #define VPIDR p15, 4, c0, c0, 0 521 #define VMPIDR p15, 4, c0, c0, 5 522 #define ISR p15, 0, c12, c1, 0 523 #define CLIDR p15, 1, c0, c0, 1 524 #define CSSELR p15, 2, c0, c0, 0 525 #define CCSIDR p15, 1, c0, c0, 0 526 #define HTCR p15, 4, c2, c0, 2 527 #define HMAIR0 p15, 4, c10, c2, 0 528 #define ATS1CPR p15, 0, c7, c8, 0 529 #define ATS1HR p15, 4, c7, c8, 0 530 #define DBGOSDLR p14, 0, c1, c3, 4 531 532 /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ 533 #define HDCR p15, 4, c1, c1, 1 534 #define PMCR p15, 0, c9, c12, 0 535 #define CNTHP_TVAL p15, 4, c14, c2, 0 536 #define CNTHP_CTL p15, 4, c14, c2, 1 537 538 /* AArch32 coproc registers for 32bit MMU descriptor support */ 539 #define PRRR p15, 0, c10, c2, 0 540 #define NMRR p15, 0, c10, c2, 1 541 #define DACR p15, 0, c3, c0, 0 542 543 /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ 544 #define ICC_IAR1 p15, 0, c12, c12, 0 545 #define ICC_IAR0 p15, 0, c12, c8, 0 546 #define ICC_EOIR1 p15, 0, c12, c12, 1 547 #define ICC_EOIR0 p15, 0, c12, c8, 1 548 #define ICC_HPPIR1 p15, 0, c12, c12, 2 549 #define ICC_HPPIR0 p15, 0, c12, c8, 2 550 #define ICC_BPR1 p15, 0, c12, c12, 3 551 #define ICC_BPR0 p15, 0, c12, c8, 3 552 #define ICC_DIR p15, 0, c12, c11, 1 553 #define ICC_PMR p15, 0, c4, c6, 0 554 #define ICC_RPR p15, 0, c12, c11, 3 555 #define ICC_CTLR p15, 0, c12, c12, 4 556 #define ICC_MCTLR p15, 6, c12, c12, 4 557 #define ICC_SRE p15, 0, c12, c12, 5 558 #define ICC_HSRE p15, 4, c12, c9, 5 559 #define ICC_MSRE p15, 6, c12, c12, 5 560 #define ICC_IGRPEN0 p15, 0, c12, c12, 6 561 #define ICC_IGRPEN1 p15, 0, c12, c12, 7 562 #define ICC_MGRPEN1 p15, 6, c12, c12, 7 563 564 /* 64 bit system register defines The format is: coproc, opt1, CRm */ 565 #define TTBR0_64 p15, 0, c2 566 #define TTBR1_64 p15, 1, c2 567 #define CNTVOFF_64 p15, 4, c14 568 #define VTTBR_64 p15, 6, c2 569 #define CNTPCT_64 p15, 0, c14 570 #define HTTBR_64 p15, 4, c2 571 #define CNTHP_CVAL_64 p15, 6, c14 572 #define PAR_64 p15, 0, c7 573 574 /* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */ 575 #define ICC_SGI1R_EL1_64 p15, 0, c12 576 #define ICC_ASGI1R_EL1_64 p15, 1, c12 577 #define ICC_SGI0R_EL1_64 p15, 2, c12 578 579 /******************************************************************************* 580 * Definitions of MAIR encodings for device and normal memory 581 ******************************************************************************/ 582 /* 583 * MAIR encodings for device memory attributes. 584 */ 585 #define MAIR_DEV_nGnRnE U(0x0) 586 #define MAIR_DEV_nGnRE U(0x4) 587 #define MAIR_DEV_nGRE U(0x8) 588 #define MAIR_DEV_GRE U(0xc) 589 590 /* 591 * MAIR encodings for normal memory attributes. 592 * 593 * Cache Policy 594 * WT: Write Through 595 * WB: Write Back 596 * NC: Non-Cacheable 597 * 598 * Transient Hint 599 * NTR: Non-Transient 600 * TR: Transient 601 * 602 * Allocation Policy 603 * RA: Read Allocate 604 * WA: Write Allocate 605 * RWA: Read and Write Allocate 606 * NA: No Allocation 607 */ 608 #define MAIR_NORM_WT_TR_WA U(0x1) 609 #define MAIR_NORM_WT_TR_RA U(0x2) 610 #define MAIR_NORM_WT_TR_RWA U(0x3) 611 #define MAIR_NORM_NC U(0x4) 612 #define MAIR_NORM_WB_TR_WA U(0x5) 613 #define MAIR_NORM_WB_TR_RA U(0x6) 614 #define MAIR_NORM_WB_TR_RWA U(0x7) 615 #define MAIR_NORM_WT_NTR_NA U(0x8) 616 #define MAIR_NORM_WT_NTR_WA U(0x9) 617 #define MAIR_NORM_WT_NTR_RA U(0xa) 618 #define MAIR_NORM_WT_NTR_RWA U(0xb) 619 #define MAIR_NORM_WB_NTR_NA U(0xc) 620 #define MAIR_NORM_WB_NTR_WA U(0xd) 621 #define MAIR_NORM_WB_NTR_RA U(0xe) 622 #define MAIR_NORM_WB_NTR_RWA U(0xf) 623 624 #define MAIR_NORM_OUTER_SHIFT U(4) 625 626 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 627 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 628 629 /* PAR fields */ 630 #define PAR_F_SHIFT U(0) 631 #define PAR_F_MASK ULL(0x1) 632 #define PAR_ADDR_SHIFT U(12) 633 #define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */ 634 635 /******************************************************************************* 636 * Definitions for system register interface to AMU for ARMv8.4 onwards 637 ******************************************************************************/ 638 #define AMCR p15, 0, c13, c2, 0 639 #define AMCFGR p15, 0, c13, c2, 1 640 #define AMCGCR p15, 0, c13, c2, 2 641 #define AMUSERENR p15, 0, c13, c2, 3 642 #define AMCNTENCLR0 p15, 0, c13, c2, 4 643 #define AMCNTENSET0 p15, 0, c13, c2, 5 644 #define AMCNTENCLR1 p15, 0, c13, c3, 0 645 #define AMCNTENSET1 p15, 0, c13, c3, 1 646 647 /* Activity Monitor Group 0 Event Counter Registers */ 648 #define AMEVCNTR00 p15, 0, c0 649 #define AMEVCNTR01 p15, 1, c0 650 #define AMEVCNTR02 p15, 2, c0 651 #define AMEVCNTR03 p15, 3, c0 652 653 /* Activity Monitor Group 0 Event Type Registers */ 654 #define AMEVTYPER00 p15, 0, c13, c6, 0 655 #define AMEVTYPER01 p15, 0, c13, c6, 1 656 #define AMEVTYPER02 p15, 0, c13, c6, 2 657 #define AMEVTYPER03 p15, 0, c13, c6, 3 658 659 /* Activity Monitor Group 1 Event Counter Registers */ 660 #define AMEVCNTR10 p15, 0, c4 661 #define AMEVCNTR11 p15, 1, c4 662 #define AMEVCNTR12 p15, 2, c4 663 #define AMEVCNTR13 p15, 3, c4 664 #define AMEVCNTR14 p15, 4, c4 665 #define AMEVCNTR15 p15, 5, c4 666 #define AMEVCNTR16 p15, 6, c4 667 #define AMEVCNTR17 p15, 7, c4 668 #define AMEVCNTR18 p15, 0, c5 669 #define AMEVCNTR19 p15, 1, c5 670 #define AMEVCNTR1A p15, 2, c5 671 #define AMEVCNTR1B p15, 3, c5 672 #define AMEVCNTR1C p15, 4, c5 673 #define AMEVCNTR1D p15, 5, c5 674 #define AMEVCNTR1E p15, 6, c5 675 #define AMEVCNTR1F p15, 7, c5 676 677 /* Activity Monitor Group 1 Event Type Registers */ 678 #define AMEVTYPER10 p15, 0, c13, c14, 0 679 #define AMEVTYPER11 p15, 0, c13, c14, 1 680 #define AMEVTYPER12 p15, 0, c13, c14, 2 681 #define AMEVTYPER13 p15, 0, c13, c14, 3 682 #define AMEVTYPER14 p15, 0, c13, c14, 4 683 #define AMEVTYPER15 p15, 0, c13, c14, 5 684 #define AMEVTYPER16 p15, 0, c13, c14, 6 685 #define AMEVTYPER17 p15, 0, c13, c14, 7 686 #define AMEVTYPER18 p15, 0, c13, c15, 0 687 #define AMEVTYPER19 p15, 0, c13, c15, 1 688 #define AMEVTYPER1A p15, 0, c13, c15, 2 689 #define AMEVTYPER1B p15, 0, c13, c15, 3 690 #define AMEVTYPER1C p15, 0, c13, c15, 4 691 #define AMEVTYPER1D p15, 0, c13, c15, 5 692 #define AMEVTYPER1E p15, 0, c13, c15, 6 693 #define AMEVTYPER1F p15, 0, c13, c15, 7 694 695 #endif /* ARCH_H */ 696