zynqmp: pm: Invalidate several clocks that Linux doesn't need to control

Linux has no reason to use these system and debug clocks and therefore
shouldn't access them. These clocks are marked as inva

zynqmp: pm: Invalidate several clocks that Linux doesn't need to control

Linux has no reason to use these system and debug clocks and therefore
shouldn't access them. These clocks are marked as invalid in order to
prevent Linux from registering and querying them.

Note that despite clocks being marked as invalid a security issue
still remains in place as there is nothing that prevents the
non-secure world from gating these clocks and that way causing
damage to the system.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Add ACPU_FULL and ACPU_HALF clocks in the invalid list

These clocks are marked as invalid in order to prevent Linux from
registering them.

Note that despite clocks being marked as inval

zynqmp: pm: Add ACPU_FULL and ACPU_HALF clocks in the invalid list

These clocks are marked as invalid in order to prevent Linux from
registering them.

Note that despite clocks being marked as invalid a security issue
still remains in place as there is nothing that prevents the
non-secure world from gating these clocks and that way halt
the whole APU subsystem.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Fix model of ACPU clocks

In the existing model for ACPU clock the mux, divider, and gate were
represented as one clock and ACPU_HALF was modelled as child of
ACPU clock. This is not corr

zynqmp: pm: Fix model of ACPU clocks

In the existing model for ACPU clock the mux, divider, and gate were
represented as one clock and ACPU_HALF was modelled as child of
ACPU clock. This is not correct. ACPU clock model contains only
mux and the divider, and it has 2 children: ACPU_FULL and ACPU_HALF
clocks which have only gates. The models of ACPU and ACPU_HALF clocks
are fixed and ACPU_FULL clock is added.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Reimplement clock get parent EEMI API

Clock get parent EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll

zynqmp: pm: Reimplement clock get parent EEMI API

Clock get parent EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock set parent API to get pre_src, post_src, div2
and bypasss, in the implementation of pm_clock_get_parent() we need to
workaround this by distinguishing two cases:
1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC,
*_POST_SRC, *_INT_MUX or *_PLL clock IDs); or
2) given clock ID is truly an on-chip clock.
For case 1) we'll map the call onto PLL-specific EEMI API with the
respective parameter ID. For case 2) the call is passed to the PMU.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Reimplement clock set parent EEMI API

Clock set parent EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll

zynqmp: pm: Reimplement clock set parent EEMI API

Clock set parent EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock set parent API to set pre_src, post_src, div2
and bypass, in the implementation of pm_clock_set_parent() we need to
workaround this by distinguishing two cases:
1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC,
*_POST_SRC, *_INT_MUX or *PLL clock IDs); or 2) given clock ID is truly
an on-chip clock.
For case 1) we'll map the call onto PLL set parameter EEMI API with the
respective parameter ID. Since clock set parent interface to EL1/2 receives
parent index (mux select value), the value is just passed to PMU.
Functions that appear to be unused after this change is made are removed.

Setting the parent of *PLL clocks, that actually model bypass, is not
possible. This is already ensured by the existing clock model having the
CLK_SET_RATE_NO_REPARENT flag. The API also doesn't allow changing the
bypass parent. Bypass is controlled only by the PMU firmware.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Cleanup for clock set/get rate EEMI API

Clock set/get rate are not implemented and will likely never be.
Remove empty function stubs.

Signed-off-by: Mirela Simonovic <mirela.simonovic@a

zynqmp: pm: Cleanup for clock set/get rate EEMI API

Clock set/get rate are not implemented and will likely never be.
Remove empty function stubs.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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zynqmp: pm: Reimplement clock get divider EEMI API

Clock get divider EEMI API is reimplemented to use system-level clock
get divider EEMI API rather than direct MMIO read/write accesses to clock
con

zynqmp: pm: Reimplement clock get divider EEMI API

Clock get divider EEMI API is reimplemented to use system-level clock
get divider EEMI API rather than direct MMIO read/write accesses to clock
control registers.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Reimplement clock set divider EEMI API

Clock set divider EEMI API is reimplemented to use system-level clock
set divider EEMI API rather than direct MMIO read/write accesses to clock
con

zynqmp: pm: Reimplement clock set divider EEMI API

Clock set divider EEMI API is reimplemented to use system-level clock
set divider EEMI API rather than direct MMIO read/write accesses to clock
control registers.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Reimplement clock get state (status) EEMI API

Clock get state EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
a

zynqmp: pm: Reimplement clock get state (status) EEMI API

Clock get state EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux is_enabled method for PLLs still uses clock get state API
get the PLL state, in the implementation of pm_clock_getstate() we need
to workaround this by distinguishing two cases: 1) if the given clock ID
corresponds to a PLL output clock ID; or 2) given clock ID is truly an
on-chip clock whose state of the gate should be returned.
For case 1) we'll call pm_api_clock_pll_getstate() implemented in
pm_api_clock.h/c. This function will query the PLL state from PMU using
the system-level PLL get mode EEMI API.
For case 2) we'll call the PMU to query the clock gate state using
system-level clock get status EEMI API.
Functions that appear to be unused after this change is made are removed.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Reimplement clock disable EEMI API

Clock disable EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll contro

zynqmp: pm: Reimplement clock disable EEMI API

Clock disable EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock disable API to reset the PLL in the
implementation of pm_clock_disable() we need to workaround this by
distinguishing two cases: 1) if the given clock ID corresponds to a PLL
output clock ID; or 2) given clock ID is truly an on-chip clock that can
be gated.
For case 1) we'll call pm_api_clock_pll_disable() implemented in
pm_api_clock.h/c. This function will reset the PLL using the system-level
PLL set mode EEMI API with the reset mode argument.
For case 2) we'll call the PMU to configure the clock gate. This is done
using system-level clock disable EEMI API.
Functions that appear to be unused after this change is made are removed.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Reimplement clock enable EEMI API

Clock enable EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control

zynqmp: pm: Reimplement clock enable EEMI API

Clock enable EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock enable API to trigger locking of the PLLs
in the pm_clock_enable() implementation we need to workaround this by
distinguishing two cases: 1) if the given clock ID corresponds to a PLL
output clock ID; or 2) given clock ID is truly an on-chip clock that can
be gated.
For case 1) we'll call pm_api_clock_pll_enable() implemented in
pm_api_clock.h/c. This function checks what is the buffered PLL mode and
calls the system-level PLL set mode EEMI API with the buffered mode value
specified as argument. Long term, if linux driver get fixed to use PLL
EEMI API to control PLLs, this case could be removed from ATF.
For case 2) we'll call the PMU to configure the clock gate. This is done
using system-level clock enable EEMI API.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Return the buffered PLL mode through IOCTL PLL get mode API

When linux calls pm_ioctl_get_pll_frac_mode() it doesn't expect the actual
mode to be read from hardware, but the value that i

zynqmp: pm: Return the buffered PLL mode through IOCTL PLL get mode API

When linux calls pm_ioctl_get_pll_frac_mode() it doesn't expect the actual
mode to be read from hardware, but the value that it is intending to
program. Therefore, we return the buffered value to linux.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Buffer the PLL mode that is set using IOCTL API

When linux calls pm_ioctl_set_pll_frac_mode() it doesn't expect the
fractional mode to be changed in hardware. Furthermore, even before th

zynqmp: pm: Buffer the PLL mode that is set using IOCTL API

When linux calls pm_ioctl_set_pll_frac_mode() it doesn't expect the
fractional mode to be changed in hardware. Furthermore, even before this
patch setting the mode which is done by writing into register takes
no effect until the PLL reset is deasserted, i.e. until linux "enables"
the PLL. To adjust the code to system-level PLL EEMI API and avoid
unnecessary IPIs that would otherwise be issued, we buffer the mode
value set via IOCTL until the PLL mode really needs to be set.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Set PLL fractional data using PLL set parameter EEMI API

Fractional data should be set using PLL set parameter EEMI API. This
stands for system-level communication (APU to PMU). Since li

zynqmp: pm: Set PLL fractional data using PLL set parameter EEMI API

Fractional data should be set using PLL set parameter EEMI API. This
stands for system-level communication (APU to PMU). Since linux
already uses a specific IOCTL function to do this and we need to
keep it that way, the pll clock ID given by linux has to be mapped
to the pll node ID that is communicated at the system-level (argument
of PLL set parameter API).
With this modification the function pm_api_clk_set_pll_frac_data is
removed from pm_api_clock.c/h because it became unused.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Get PLL fractional data using PLL get parameter EEMI API

Fractional data should be get using PLL get parameter EEMI API. This
stands for system-level communication (APU to PMU). Since li

zynqmp: pm: Get PLL fractional data using PLL get parameter EEMI API

Fractional data should be get using PLL get parameter EEMI API. This
stands for system-level communication (APU to PMU). Since linux
already uses a specific IOCTL function to do this and we need to
keep it that way, the pll clock ID given by linux has to be mapped
to the pll node ID that is communicated at the system-level (argument
of PLL get parameter API).
With this modification the function pm_api_clk_get_pll_frac_data is
removed from pm_api_clock.c/h because it became unused.
The clock enum is defined as 'enum clock_id'.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Implement PLL get mode EEMI API

This API will be used to get the currently configured PLL mode:
reset (bypassed and unlocked), integer or fractional (locked).

Signed-off-by: Mirela Simo

zynqmp: pm: Implement PLL get mode EEMI API

This API will be used to get the currently configured PLL mode:
reset (bypassed and unlocked), integer or fractional (locked).

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Implement PLL set mode EEMI API

This API will be used to set the PLL mode: reset (unlocked), integer
or fractional (locked). If reset mode is set the PM controller will
bypass the target

zynqmp: pm: Implement PLL set mode EEMI API

This API will be used to set the PLL mode: reset (unlocked), integer
or fractional (locked). If reset mode is set the PM controller will
bypass the target PLL prior to asserting the reset. If integer or
fractional mode is set the PM controller will program and trigger
locking of the PLL. If success status is returned the PLL is locked
and its bypass is deasserted. If fractional mode is set the fractional
divider (data parameter) has to have a non-zero value prior to issuing
pll set fractional mode. The caller need to ensure that the data
parameter is properly set using pll get/set parameter EEMI API.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Implement PLL get parameter EEMI API

This API will be used to get a parameter for the PLL. Parameter values
represent the values as defined in the Zynq MPSoC register reference
manual ug

zynqmp: pm: Implement PLL get parameter EEMI API

This API will be used to get a parameter for the PLL. Parameter values
represent the values as defined in the Zynq MPSoC register reference
manual ug1087.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

zynqmp: pm: Implement PLL set parameter EEMI API

This API will be used to set a parameter for the PLL. The parameter
value that is set will have effect once the PLL mode is set to integer
or fractio

zynqmp: pm: Implement PLL set parameter EEMI API

This API will be used to set a parameter for the PLL. The parameter
value that is set will have effect once the PLL mode is set to integer
or fractional mode. Parameter values represent the values as defined
in the Zynq MPSoC register reference manual ug1087.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

show more ...

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- inclu

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this proje

Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Ensure the flow through switch statements is clear

Ensure case clauses:
* Terminate with an unconditional break, return or goto statement.
* Use conditional break, return or goto statements as l

Ensure the flow through switch statements is clear

Ensure case clauses:
* Terminate with an unconditional break, return or goto statement.
* Use conditional break, return or goto statements as long as the end
of the case clause is unreachable; such case clauses must terminate
with assert(0) /* Unreachable */ or an unconditional __dead2 function
call
* Only fallthough when doing otherwise would result in less
readable/maintainable code; such case clauses must terminate with a
/* Fallthrough */ comment to make it clear this is the case and
indicate that a fallthrough is intended.

This reduces the chance of bugs appearing due to unintended flow through a
switch statement

Change-Id: I70fc2d1f4fd679042397dec12fd1982976646168
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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zynqmp: Add ATF support for Data blob encryption and decryption

This patch adds ATF support for AES data blob encrypt/decrypt.
ATF establishes a path to send the address of the structure
to the xils

zynqmp: Add ATF support for Data blob encryption and decryption

This patch adds ATF support for AES data blob encrypt/decrypt.
ATF establishes a path to send the address of the structure
to the xilsecure, so that it will pick addresses of the data
and performs the requested operation (encrypt/decrypt) and puts
the result in load address.

where structure contains
- Data blob src address
- load address
- IV address
- Key address - this will actual key addr in case of KUP
else it will be zero.
- Data-size
- Aes-op type
- KeySrc

Signed-off-by: Kalyani Akula <kalyani.akula@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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zynqmp: pm: Correct function header of clock APIs

Correct function header of pm_api_clock_getparent() and
pm_api_clock_setparent().

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Acked-by: Will

zynqmp: pm: Correct function header of clock APIs

Correct function header of pm_api_clock_getparent() and
pm_api_clock_setparent().

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Acked-by: Will Wong <WILLW@xilinx.com>

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zynqmp: pm_service: Ignore enable/disable of PLL type clocks

PLL type clock is enabled by FSBL on boot-up. PMUFW enable/disable
them based on their user count. So, it should not be handled from ATF.

zynqmp: pm_service: Ignore enable/disable of PLL type clocks

PLL type clock is enabled by FSBL on boot-up. PMUFW enable/disable
them based on their user count. So, it should not be handled from ATF.

Put PLL type clock into bypass and reset mode only while changing
PLL rate (FBDIV).

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

show more ...