1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arm_def.h> 9 #include <arm_xlat_tables.h> 10 #include <assert.h> 11 #include <bl1.h> 12 #include <bl_common.h> 13 #include <plat_arm.h> 14 #include <platform.h> 15 #include <platform_def.h> 16 #include <sp805.h> 17 #include <utils.h> 18 #include "../../../bl1/bl1_private.h" 19 20 /* Weak definitions may be overridden in specific ARM standard platform */ 21 #pragma weak bl1_early_platform_setup 22 #pragma weak bl1_plat_arch_setup 23 #pragma weak bl1_platform_setup 24 #pragma weak bl1_plat_sec_mem_layout 25 #pragma weak bl1_plat_prepare_exit 26 #pragma weak bl1_plat_get_next_image_id 27 #pragma weak plat_arm_bl1_fwu_needed 28 29 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \ 30 bl1_tzram_layout.total_base, \ 31 bl1_tzram_layout.total_size, \ 32 MT_MEMORY | MT_RW | MT_SECURE) 33 /* 34 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 35 * otherwise one region is defined containing both 36 */ 37 #if SEPARATE_CODE_AND_RODATA 38 #define MAP_BL1_RO MAP_REGION_FLAT( \ 39 BL_CODE_BASE, \ 40 BL1_CODE_END - BL_CODE_BASE, \ 41 MT_CODE | MT_SECURE), \ 42 MAP_REGION_FLAT( \ 43 BL1_RO_DATA_BASE, \ 44 BL1_RO_DATA_END \ 45 - BL_RO_DATA_BASE, \ 46 MT_RO_DATA | MT_SECURE) 47 #else 48 #define MAP_BL1_RO MAP_REGION_FLAT( \ 49 BL_CODE_BASE, \ 50 BL1_CODE_END - BL_CODE_BASE, \ 51 MT_CODE | MT_SECURE) 52 #endif 53 54 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 55 static meminfo_t bl1_tzram_layout; 56 57 struct meminfo *bl1_plat_sec_mem_layout(void) 58 { 59 return &bl1_tzram_layout; 60 } 61 62 /******************************************************************************* 63 * BL1 specific platform actions shared between ARM standard platforms. 64 ******************************************************************************/ 65 void arm_bl1_early_platform_setup(void) 66 { 67 68 #if !ARM_DISABLE_TRUSTED_WDOG 69 /* Enable watchdog */ 70 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 71 #endif 72 73 /* Initialize the console to provide early debug support */ 74 arm_console_boot_init(); 75 76 /* Allow BL1 to see the whole Trusted RAM */ 77 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; 78 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; 79 80 #if !LOAD_IMAGE_V2 81 /* Calculate how much RAM BL1 is using and how much remains free */ 82 bl1_tzram_layout.free_base = ARM_BL_RAM_BASE; 83 bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE; 84 reserve_mem(&bl1_tzram_layout.free_base, 85 &bl1_tzram_layout.free_size, 86 BL1_RAM_BASE, 87 BL1_RAM_LIMIT - BL1_RAM_BASE); 88 #endif /* LOAD_IMAGE_V2 */ 89 } 90 91 void bl1_early_platform_setup(void) 92 { 93 arm_bl1_early_platform_setup(); 94 95 /* 96 * Initialize Interconnect for this cluster during cold boot. 97 * No need for locks as no other CPU is active. 98 */ 99 plat_arm_interconnect_init(); 100 /* 101 * Enable Interconnect coherency for the primary CPU's cluster. 102 */ 103 plat_arm_interconnect_enter_coherency(); 104 } 105 106 /****************************************************************************** 107 * Perform the very early platform specific architecture setup shared between 108 * ARM standard platforms. This only does basic initialization. Later 109 * architectural setup (bl1_arch_setup()) does not do anything platform 110 * specific. 111 *****************************************************************************/ 112 void arm_bl1_plat_arch_setup(void) 113 { 114 #if USE_COHERENT_MEM 115 /* ARM platforms dont use coherent memory in BL1 */ 116 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 117 #endif 118 119 const mmap_region_t bl_regions[] = { 120 MAP_BL1_TOTAL, 121 MAP_BL1_RO, 122 #if USE_ROMLIB 123 ARM_MAP_ROMLIB_CODE, 124 ARM_MAP_ROMLIB_DATA, 125 #endif 126 {0} 127 }; 128 129 arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); 130 #ifdef AARCH32 131 enable_mmu_svc_mon(0); 132 #else 133 enable_mmu_el3(0); 134 #endif /* AARCH32 */ 135 136 arm_setup_romlib(); 137 } 138 139 void bl1_plat_arch_setup(void) 140 { 141 arm_bl1_plat_arch_setup(); 142 } 143 144 /* 145 * Perform the platform specific architecture setup shared between 146 * ARM standard platforms. 147 */ 148 void arm_bl1_platform_setup(void) 149 { 150 /* Initialise the IO layer and register platform IO devices */ 151 plat_arm_io_setup(); 152 #if LOAD_IMAGE_V2 153 arm_load_tb_fw_config(); 154 #if TRUSTED_BOARD_BOOT 155 /* Share the Mbed TLS heap info with other images */ 156 arm_bl1_set_mbedtls_heap(); 157 #endif /* TRUSTED_BOARD_BOOT */ 158 #endif /* LOAD_IMAGE_V2 */ 159 /* 160 * Allow access to the System counter timer module and program 161 * counter frequency for non secure images during FWU 162 */ 163 arm_configure_sys_timer(); 164 write_cntfrq_el0(plat_get_syscnt_freq2()); 165 } 166 167 void bl1_platform_setup(void) 168 { 169 arm_bl1_platform_setup(); 170 } 171 172 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 173 { 174 #if !ARM_DISABLE_TRUSTED_WDOG 175 /* Disable watchdog before leaving BL1 */ 176 sp805_stop(ARM_SP805_TWDG_BASE); 177 #endif 178 179 #ifdef EL3_PAYLOAD_BASE 180 /* 181 * Program the EL3 payload's entry point address into the CPUs mailbox 182 * in order to release secondary CPUs from their holding pen and make 183 * them jump there. 184 */ 185 plat_arm_program_trusted_mailbox(ep_info->pc); 186 dsbsy(); 187 sev(); 188 #endif 189 } 190 191 /* 192 * On Arm platforms, the FWU process is triggered when the FIP image has 193 * been tampered with. 194 */ 195 int plat_arm_bl1_fwu_needed(void) 196 { 197 return (arm_io_is_toc_valid() != 1); 198 } 199 200 /******************************************************************************* 201 * The following function checks if Firmware update is needed, 202 * by checking if TOC in FIP image is valid or not. 203 ******************************************************************************/ 204 unsigned int bl1_plat_get_next_image_id(void) 205 { 206 if (plat_arm_bl1_fwu_needed() != 0) 207 return NS_BL1U_IMAGE_ID; 208 209 return BL2_IMAGE_ID; 210 } 211