| 98859b99 | 29-Jan-2025 |
Sammit Joshi <sammit.joshi@arm.com> |
feat(per-cpu): integrate per-cpu framework into BL31/BL32
Integrate per-cpu support into BL31/BL32 by extending the following
areas:
Zero-initialization: Treats per-cpu sections like .bss and clear
feat(per-cpu): integrate per-cpu framework into BL31/BL32
Integrate per-cpu support into BL31/BL32 by extending the following
areas:
Zero-initialization: Treats per-cpu sections like .bss and clears them
during early C runtime initialization. For platforms that enable
NUMA_AWARE_PER_CPU, invokes a platform hook to zero-initialize
node-specific per-cpu regions.
Cache maintenance: Extends the BL31 exit path to clean dcache lines
covering the per-cpu region, ensuring data written by the primary core
is visible to secondary cores.
tpidr_el3 setup: Initializes tpidr_el3 with the base address of the
current CPU’s per-cpu section. This allows per-cpu framework to
resolve local cpu accesses efficiently.
The percpu_data object is currently stored in tpidr_el3. Since the
per-cpu framework will use tpidr_el3 for this-cpu access, percpu_data
must be migrated to avoid conflict. This commit moves percpu_data to
the per-cpu framework.
Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Iff0c2e1f8c0ebd25c4bb0b09bfe15dd4fbe20561
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| 3fabca72 | 18-Feb-2025 |
Harrison Mutai <harrison.mutai@arm.com> |
feat(bl32): enable r3 usage for boot args
`r3` is used to pass the base address of the transfer list. Make sure we
update the context structure with this register value so it is populated
with this
feat(bl32): enable r3 usage for boot args
`r3` is used to pass the base address of the transfer list. Make sure we
update the context structure with this register value so it is populated
with this information prior to executing the next stage.
Change-Id: Ie1eedbd2eb68b592df30779625691e8975d987bf
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| 3c225878 | 01-May-2024 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(smccc): refactor vendor-el3 build
Currently we are building vendor-specific EL3 by default similar to
arm-sip but unfortunately this causes few troubles for now.
- Few model builds configu
refactor(smccc): refactor vendor-el3 build
Currently we are building vendor-specific EL3 by default similar to
arm-sip but unfortunately this causes few troubles for now.
- Few model builds configuration like 'fvp-dynamiq-aarch64-only'
is on 256KB SRAM border and this configuration is also run on some
older models like A710 and N2, so we cant move them to 384KB SRAM size
and to new model.
- Not able to move some older model builds to new model due to known
issue in power modelling in some of the models, making it difficult to
transition.
However vendor-specific EL3 is currently using PMF, DEBUGFS so building
the vendor EL3 support only when any of this sub-service is built also
helps to avoid bloating BL31 image size in certain configurations.
However this is not end of road, we will monitor how vendor-specific EL3
grows with sub-service and if needed will make this interface to built
by default like arm-sip range. Also this doesn't stop platform owners to
make vendor-specific EL3 to be enabled by default for their platform
configuration.
Change-Id: I23322574bdeb7179441a580ad4f093216a948bbf
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| 94e1be2b | 02-Apr-2023 |
Stephan Gerhold <stephan@gerhold.net> |
feat(bl32): print entry point before exiting SP_MIN
BL31 prints information about the entry point in the normal world
before exiting, but for some reason SP_MIN does not do that. Add the
missing cal
feat(bl32): print entry point before exiting SP_MIN
BL31 prints information about the entry point in the normal world
before exiting, but for some reason SP_MIN does not do that. Add the
missing call to print_entry_point_info() for more consistency.
Change-Id: I2f4961fec57fcc9955cd15652d4ceba3bbb32375
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
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| 56055e87 | 17-Apr-2023 |
Stephan Gerhold <stephan@gerhold.net> |
fix(bl32): avoid clearing argument registers in RESET_TO_SP_MIN case
RESET_TO_SP_MIN is also used by platforms with a non TF-A bootloader,
in which case there might be platform-specific arguments pa
fix(bl32): avoid clearing argument registers in RESET_TO_SP_MIN case
RESET_TO_SP_MIN is also used by platforms with a non TF-A bootloader,
in which case there might be platform-specific arguments passed in the
CPU registers. At the moment these are cleared and cannot be used by
the platform layer.
For BL31 this was recently changed in "fix(bl31): avoid clearing of
argument registers in RESET_TO_BL31 case", but on AArch32 SP_MIN still
has the old behavior.
Make this consistent by preserving the registers in SP_MIN as well
and use the chance to clarify the existing comments a bit.
Change-Id: I0039c72477249eed76c3da23cb4f10ac59b310d0
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
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