1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <drivers/auth/auth_mod.h> 18 #include <drivers/auth/crypto_mod.h> 19 #include <drivers/console.h> 20 #include <lib/bootmarker_capture.h> 21 #include <lib/cpus/errata.h> 22 #include <lib/pmf/pmf.h> 23 #include <lib/utils.h> 24 #include <plat/common/platform.h> 25 #include <smccc_helpers.h> 26 #include <tools_share/uuid.h> 27 28 #include "bl1_private.h" 29 30 static void bl1_load_bl2(void); 31 32 #if ENABLE_PAUTH 33 uint64_t bl1_apiakey[2]; 34 #endif 35 36 #if ENABLE_RUNTIME_INSTRUMENTATION 37 PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID, 38 BL_TOTAL_IDS, PMF_DUMP_ENABLE) 39 #endif 40 41 /******************************************************************************* 42 * Helper utility to calculate the BL2 memory layout taking into consideration 43 * the BL1 RW data assuming that it is at the top of the memory layout. 44 ******************************************************************************/ 45 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 46 meminfo_t *bl2_mem_layout) 47 { 48 assert(bl1_mem_layout != NULL); 49 assert(bl2_mem_layout != NULL); 50 51 /* 52 * Remove BL1 RW data from the scope of memory visible to BL2. 53 * This is assuming BL1 RW data is at the top of bl1_mem_layout. 54 */ 55 assert(BL1_RW_BASE > bl1_mem_layout->total_base); 56 bl2_mem_layout->total_base = bl1_mem_layout->total_base; 57 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; 58 59 flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t)); 60 } 61 62 /******************************************************************************* 63 * Setup function for BL1. 64 ******************************************************************************/ 65 void bl1_setup(void) 66 { 67 /* Enable early console if EARLY_CONSOLE flag is enabled */ 68 plat_setup_early_console(); 69 70 /* Perform early platform-specific setup */ 71 bl1_early_platform_setup(); 72 73 /* Perform late platform-specific setup */ 74 bl1_plat_arch_setup(); 75 76 #if CTX_INCLUDE_PAUTH_REGS 77 /* 78 * Assert that the ARMv8.3-PAuth registers are present or an access 79 * fault will be triggered when they are being saved or restored. 80 */ 81 assert(is_armv8_3_pauth_present()); 82 #endif /* CTX_INCLUDE_PAUTH_REGS */ 83 } 84 85 /******************************************************************************* 86 * Function to perform late architectural and platform specific initialization. 87 * It also queries the platform to load and run next BL image. Only called 88 * by the primary cpu after a cold boot. 89 ******************************************************************************/ 90 void bl1_main(void) 91 { 92 unsigned int image_id; 93 94 #if ENABLE_RUNTIME_INSTRUMENTATION 95 PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_ENTRY, PMF_CACHE_MAINT); 96 #endif 97 98 /* Announce our arrival */ 99 NOTICE(FIRMWARE_WELCOME_STR); 100 NOTICE("BL1: %s\n", version_string); 101 NOTICE("BL1: %s\n", build_message); 102 103 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT); 104 105 print_errata_status(); 106 107 #if ENABLE_ASSERTIONS 108 u_register_t val; 109 /* 110 * Ensure that MMU/Caches and coherency are turned on 111 */ 112 #ifdef __aarch64__ 113 val = read_sctlr_el3(); 114 #else 115 val = read_sctlr(); 116 #endif 117 assert((val & SCTLR_M_BIT) != 0); 118 assert((val & SCTLR_C_BIT) != 0); 119 assert((val & SCTLR_I_BIT) != 0); 120 /* 121 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the 122 * provided platform value 123 */ 124 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; 125 /* 126 * If CWG is zero, then no CWG information is available but we can 127 * at least check the platform value is less than the architectural 128 * maximum. 129 */ 130 if (val != 0) 131 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); 132 else 133 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); 134 #endif /* ENABLE_ASSERTIONS */ 135 136 /* Perform remaining generic architectural setup from EL3 */ 137 bl1_arch_setup(); 138 139 crypto_mod_init(); 140 141 /* Initialize authentication module */ 142 auth_mod_init(); 143 144 /* Initialize the measured boot */ 145 bl1_plat_mboot_init(); 146 147 /* Perform platform setup in BL1. */ 148 bl1_platform_setup(); 149 150 #if ENABLE_PAUTH 151 /* Store APIAKey_EL1 key */ 152 bl1_apiakey[0] = read_apiakeylo_el1(); 153 bl1_apiakey[1] = read_apiakeyhi_el1(); 154 #endif /* ENABLE_PAUTH */ 155 156 /* Get the image id of next image to load and run. */ 157 image_id = bl1_plat_get_next_image_id(); 158 159 /* 160 * We currently interpret any image id other than 161 * BL2_IMAGE_ID as the start of firmware update. 162 */ 163 if (image_id == BL2_IMAGE_ID) 164 bl1_load_bl2(); 165 else 166 NOTICE("BL1-FWU: *******FWU Process Started*******\n"); 167 168 /* Teardown the measured boot driver */ 169 bl1_plat_mboot_finish(); 170 171 bl1_prepare_next_image(image_id); 172 173 #if ENABLE_RUNTIME_INSTRUMENTATION 174 PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_EXIT, PMF_CACHE_MAINT); 175 #endif 176 177 console_flush(); 178 } 179 180 /******************************************************************************* 181 * This function locates and loads the BL2 raw binary image in the trusted SRAM. 182 * Called by the primary cpu after a cold boot. 183 * TODO: Add support for alternative image load mechanism e.g using virtio/elf 184 * loader etc. 185 ******************************************************************************/ 186 static void bl1_load_bl2(void) 187 { 188 image_desc_t *desc; 189 image_info_t *info; 190 int err; 191 192 /* Get the image descriptor */ 193 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); 194 assert(desc != NULL); 195 196 /* Get the image info */ 197 info = &desc->image_info; 198 INFO("BL1: Loading BL2\n"); 199 200 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID); 201 if (err != 0) { 202 ERROR("Failure in pre image load handling of BL2 (%d)\n", err); 203 plat_error_handler(err); 204 } 205 206 err = load_auth_image(BL2_IMAGE_ID, info); 207 if (err != 0) { 208 ERROR("Failed to load BL2 firmware.\n"); 209 plat_error_handler(err); 210 } 211 212 /* Allow platform to handle image information. */ 213 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID); 214 if (err != 0) { 215 ERROR("Failure in post image load handling of BL2 (%d)\n", err); 216 plat_error_handler(err); 217 } 218 219 NOTICE("BL1: Booting BL2\n"); 220 } 221 222 /******************************************************************************* 223 * Function called just before handing over to the next BL to inform the user 224 * about the boot progress. In debug mode, also print details about the BL 225 * image's execution context. 226 ******************************************************************************/ 227 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info) 228 { 229 #ifdef __aarch64__ 230 NOTICE("BL1: Booting BL31\n"); 231 #else 232 NOTICE("BL1: Booting BL32\n"); 233 #endif /* __aarch64__ */ 234 print_entry_point_info(bl_ep_info); 235 } 236 237 #if SPIN_ON_BL1_EXIT 238 void print_debug_loop_message(void) 239 { 240 NOTICE("BL1: Debug loop, spinning forever\n"); 241 NOTICE("BL1: Please connect the debugger to continue\n"); 242 } 243 #endif 244 245 /******************************************************************************* 246 * Top level handler for servicing BL1 SMCs. 247 ******************************************************************************/ 248 u_register_t bl1_smc_handler(unsigned int smc_fid, 249 u_register_t x1, 250 u_register_t x2, 251 u_register_t x3, 252 u_register_t x4, 253 void *cookie, 254 void *handle, 255 unsigned int flags) 256 { 257 /* BL1 Service UUID */ 258 DEFINE_SVC_UUID2(bl1_svc_uid, 259 U(0xd46739fd), 0xcb72, 0x9a4d, 0xb5, 0x75, 260 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a); 261 262 263 #if TRUSTED_BOARD_BOOT 264 /* 265 * Dispatch FWU calls to FWU SMC handler and return its return 266 * value 267 */ 268 if (is_fwu_fid(smc_fid)) { 269 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie, 270 handle, flags); 271 } 272 #endif 273 274 switch (smc_fid) { 275 case BL1_SMC_CALL_COUNT: 276 SMC_RET1(handle, BL1_NUM_SMC_CALLS); 277 278 case BL1_SMC_UID: 279 SMC_UUID_RET(handle, bl1_svc_uid); 280 281 case BL1_SMC_VERSION: 282 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER); 283 284 default: 285 WARN("Unimplemented BL1 SMC Call: 0x%x\n", smc_fid); 286 SMC_RET1(handle, SMC_UNK); 287 } 288 } 289 290 /******************************************************************************* 291 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI 292 * compliance when invoking bl1_smc_handler. 293 ******************************************************************************/ 294 u_register_t bl1_smc_wrapper(uint32_t smc_fid, 295 void *cookie, 296 void *handle, 297 unsigned int flags) 298 { 299 u_register_t x1, x2, x3, x4; 300 301 assert(handle != NULL); 302 303 get_smc_params_from_ctx(handle, x1, x2, x3, x4); 304 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 305 } 306