1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLAT_ARM_H 7 #define PLAT_ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 12 #include <common/desc_image_load.h> 13 #include <drivers/arm/tzc_common.h> 14 #include <lib/bakery_lock.h> 15 #include <lib/cassert.h> 16 #include <lib/el3_runtime/cpu_data.h> 17 #include <lib/gpt_rme/gpt_rme.h> 18 #include <lib/spinlock.h> 19 #include <lib/transfer_list.h> 20 #include <lib/utils_def.h> 21 #include <lib/xlat_tables/xlat_tables_compat.h> 22 23 /******************************************************************************* 24 * Forward declarations 25 ******************************************************************************/ 26 struct meminfo; 27 struct image_info; 28 struct bl_params; 29 30 typedef struct arm_tzc_regions_info { 31 unsigned long long base; 32 unsigned long long end; 33 unsigned int sec_attr; 34 unsigned int nsaid_permissions; 35 } arm_tzc_regions_info_t; 36 37 typedef struct arm_gpt_info { 38 pas_region_t *pas_region_base; 39 unsigned int pas_region_count; 40 uintptr_t l0_base; 41 uintptr_t l1_base; 42 size_t l0_size; 43 size_t l1_size; 44 gpccr_pps_e pps; 45 gpccr_pgs_e pgs; 46 } arm_gpt_info_t; 47 48 /******************************************************************************* 49 * Default mapping definition of the TrustZone Controller for ARM standard 50 * platforms. 51 * Configure: 52 * - Region 0 with no access; 53 * - Region 1 with secure access only; 54 * - the remaining DRAM regions access from the given Non-Secure masters. 55 ******************************************************************************/ 56 57 #if ENABLE_RME 58 #define ARM_TZC_RME_REGIONS_DEF \ 59 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ 60 {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ 61 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 62 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 63 /* Realm and Shared area share the same PAS */ \ 64 {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 65 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 66 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 67 PLAT_ARM_TZC_NS_DEV_ACCESS} 68 #endif 69 70 #if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) 71 #define ARM_TZC_REGIONS_DEF \ 72 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 73 TZC_REGION_S_RDWR, 0}, \ 74 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 75 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 76 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 77 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 78 {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \ 79 PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ 80 PLAT_ARM_TZC_NS_DEV_ACCESS} 81 82 #elif ENABLE_RME 83 #if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 84 MEASURED_BOOT 85 #define ARM_TZC_REGIONS_DEF \ 86 ARM_TZC_RME_REGIONS_DEF, \ 87 {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \ 88 TZC_REGION_S_RDWR, 0} 89 #else 90 #define ARM_TZC_REGIONS_DEF \ 91 ARM_TZC_RME_REGIONS_DEF 92 #endif 93 94 #else 95 #define ARM_TZC_REGIONS_DEF \ 96 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 97 TZC_REGION_S_RDWR, 0}, \ 98 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 99 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 100 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 101 PLAT_ARM_TZC_NS_DEV_ACCESS} 102 #endif 103 104 #define ARM_CASSERT_MMAP \ 105 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 106 assert_plat_arm_mmap_mismatch); \ 107 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 108 <= MAX_MMAP_REGIONS, \ 109 assert_max_mmap_regions); 110 111 void arm_setup_romlib(void); 112 113 #if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) 114 /* 115 * Use this macro to instantiate lock before it is used in below 116 * arm_lock_xxx() macros 117 */ 118 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 119 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 120 121 #if !HW_ASSISTED_COHERENCY 122 #define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) 123 #else 124 #define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock 125 #endif 126 #define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) 127 128 /* 129 * These are wrapper macros to the Coherent Memory Bakery Lock API. 130 */ 131 #define arm_lock_init() bakery_lock_init(&arm_lock) 132 #define arm_lock_get() bakery_lock_get(&arm_lock) 133 #define arm_lock_release() bakery_lock_release(&arm_lock) 134 135 #else 136 137 /* 138 * Empty macros for all other BL stages other than BL31 and BL32 139 */ 140 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 141 #define ARM_LOCK_GET_INSTANCE 0 142 #define arm_lock_init() 143 #define arm_lock_get() 144 #define arm_lock_release() 145 146 #endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ 147 148 #if ARM_RECOM_STATE_ID_ENC 149 /* 150 * Macros used to parse state information from State-ID if it is using the 151 * recommended encoding for State-ID. 152 */ 153 #define ARM_LOCAL_PSTATE_WIDTH 4 154 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 155 156 #if PSCI_OS_INIT_MODE 157 #define ARM_LAST_AT_PLVL_MASK (ARM_LOCAL_PSTATE_MASK << \ 158 (ARM_LOCAL_PSTATE_WIDTH * \ 159 (PLAT_MAX_PWR_LVL + 1))) 160 #endif /* __PSCI_OS_INIT_MODE__ */ 161 162 /* Macros to construct the composite power state */ 163 164 /* Make composite power state parameter till power level 0 */ 165 #if PSCI_EXTENDED_STATE_ID 166 167 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 168 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 169 #else 170 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 171 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 172 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 173 ((type) << PSTATE_TYPE_SHIFT)) 174 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 175 176 /* Make composite power state parameter till power level 1 */ 177 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 178 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 179 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 180 181 /* Make composite power state parameter till power level 2 */ 182 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 183 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 184 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 185 186 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 187 188 /* ARM State switch error codes */ 189 #define STATE_SW_E_PARAM (-2) 190 #define STATE_SW_E_DENIED (-3) 191 192 /* plat_get_rotpk_info() flags */ 193 #define ARM_ROTPK_REGS_ID 1 194 #define ARM_ROTPK_DEVEL_RSA_ID 2 195 #define ARM_ROTPK_DEVEL_ECDSA_ID 3 196 #define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4 197 #define ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID 5 198 199 #define ARM_USE_DEVEL_ROTPK \ 200 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ 201 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \ 202 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) || \ 203 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID) 204 205 /* IO storage utility functions */ 206 int arm_io_setup(void); 207 208 /* Set image specification in IO block policy */ 209 int arm_set_image_source(unsigned int image_id, const char *part_name, 210 uintptr_t *dev_handle, uintptr_t *image_spec); 211 void arm_set_fip_addr(uint32_t active_fw_bank_idx); 212 213 /* Security utility functions */ 214 void arm_tzc400_setup(uintptr_t tzc_base, 215 const arm_tzc_regions_info_t *tzc_regions); 216 struct tzc_dmc500_driver_data; 217 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 218 const arm_tzc_regions_info_t *tzc_regions); 219 220 /* Console utility functions */ 221 void arm_console_boot_init(void); 222 void arm_console_boot_end(void); 223 void arm_console_runtime_init(void); 224 void arm_console_runtime_end(void); 225 226 /* Systimer utility function */ 227 void arm_configure_sys_timer(void); 228 229 /* PM utility functions */ 230 int arm_validate_power_state(unsigned int power_state, 231 psci_power_state_t *req_state); 232 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 233 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 234 void arm_system_pwr_domain_save(void); 235 void arm_system_pwr_domain_resume(void); 236 int arm_psci_read_mem_protect(int *enabled); 237 int arm_nor_psci_write_mem_protect(int val); 238 void arm_nor_psci_do_static_mem_protect(void); 239 void arm_nor_psci_do_dyn_mem_protect(void); 240 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 241 242 /* Topology utility function */ 243 int arm_check_mpidr(u_register_t mpidr); 244 245 /* BL1 utility functions */ 246 void arm_bl1_early_platform_setup(void); 247 void arm_bl1_platform_setup(void); 248 void arm_bl1_plat_arch_setup(void); 249 250 /* BL2 utility functions */ 251 void arm_bl2_early_platform_setup(uintptr_t fw_config, struct meminfo *mem_layout); 252 void arm_bl2_platform_setup(void); 253 void arm_bl2_plat_arch_setup(void); 254 uint32_t arm_get_spsr_for_bl32_entry(void); 255 uint32_t arm_get_spsr_for_bl33_entry(void); 256 int arm_bl2_plat_handle_post_image_load(unsigned int image_id); 257 int arm_bl2_handle_post_image_load(unsigned int image_id); 258 struct bl_params *arm_get_next_bl_params(void); 259 void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node); 260 261 /* BL2 at EL3 functions */ 262 void arm_bl2_el3_early_platform_setup(void); 263 void arm_bl2_el3_plat_arch_setup(void); 264 265 /* BL2U utility functions */ 266 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 267 void *plat_info); 268 void arm_bl2u_platform_setup(void); 269 void arm_bl2u_plat_arch_setup(void); 270 271 /* BL31 utility functions */ 272 #if TRANSFER_LIST 273 void arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1, 274 u_register_t arg2, u_register_t arg3); 275 #else 276 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 277 uintptr_t hw_config, void *plat_params_from_bl2); 278 #endif 279 void arm_bl31_platform_setup(void); 280 void arm_bl31_plat_runtime_setup(void); 281 void arm_bl31_plat_arch_setup(void); 282 283 /* Firmware Handoff utility functions */ 284 void arm_transfer_list_dyn_cfg_init(struct transfer_list_header *secure_tl); 285 void arm_transfer_list_populate_ep_info(bl_mem_params_node_t *next_param_node, 286 struct transfer_list_header *secure_tl, 287 struct transfer_list_header *ns_tl); 288 void arm_transfer_list_copy_hw_config(struct transfer_list_header *secure_tl, 289 struct transfer_list_header *ns_tl); 290 291 /* TSP utility functions */ 292 void arm_tsp_early_platform_setup(void); 293 294 /* SP_MIN utility functions */ 295 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 296 uintptr_t hw_config, void *plat_params_from_bl2); 297 void arm_sp_min_plat_runtime_setup(void); 298 void arm_sp_min_plat_arch_setup(void); 299 300 /* FIP TOC validity check */ 301 bool arm_io_is_toc_valid(void); 302 303 /* Utility functions for Dynamic Config */ 304 305 void arm_bl1_set_mbedtls_heap(void); 306 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); 307 308 #if IMAGE_BL2 309 void arm_bl2_dyn_cfg_init(void); 310 #endif /* IMAGE_BL2 */ 311 312 #if MEASURED_BOOT 313 #if DICE_PROTECTION_ENVIRONMENT 314 int arm_set_nt_fw_info(int *ctx_handle); 315 int arm_set_tb_fw_info(int *ctx_handle); 316 int arm_get_tb_fw_info(int *ctx_handle); 317 #else 318 /* Specific to event log backend */ 319 int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size); 320 int arm_set_nt_fw_info( 321 /* 322 * Currently OP-TEE does not support reading DTBs from Secure memory 323 * and this option should be removed when feature is supported. 324 */ 325 #ifdef SPD_opteed 326 uintptr_t log_addr, 327 #endif 328 size_t log_size, uintptr_t *ns_log_addr); 329 int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size, 330 size_t log_max_size); 331 int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size, 332 size_t *log_max_size); 333 #endif /* DICE_PROTECTION_ENVIRONMENT */ 334 #endif /* MEASURED_BOOT */ 335 336 /* 337 * Free the memory storing initialization code only used during an images boot 338 * time so it can be reclaimed for runtime data 339 */ 340 void arm_free_init_memory(void); 341 342 /* 343 * Make the higher level translation tables read-only 344 */ 345 void arm_xlat_make_tables_readonly(void); 346 347 /* 348 * Mandatory functions required in ARM standard platforms 349 */ 350 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 351 void plat_arm_gic_driver_init(void); 352 void plat_arm_gic_init(void); 353 void plat_arm_gic_cpuif_enable(void); 354 void plat_arm_gic_cpuif_disable(void); 355 void plat_arm_gic_redistif_on(void); 356 void plat_arm_gic_redistif_off(void); 357 void plat_arm_gic_pcpu_init(void); 358 void plat_arm_gic_save(void); 359 void plat_arm_gic_resume(void); 360 void plat_arm_security_setup(void); 361 void plat_arm_pwrc_setup(void); 362 void plat_arm_interconnect_init(void); 363 void plat_arm_interconnect_enter_coherency(void); 364 void plat_arm_interconnect_exit_coherency(void); 365 void plat_arm_program_trusted_mailbox(uintptr_t address); 366 bool plat_arm_bl1_fwu_needed(void); 367 __dead2 void plat_arm_error_handler(int err); 368 __dead2 void plat_arm_system_reset(void); 369 370 /* 371 * Optional functions in ARM standard platforms 372 */ 373 void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); 374 int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, 375 unsigned int *flags); 376 int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, 377 unsigned int *flags); 378 int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, 379 unsigned int *flags); 380 int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, 381 unsigned int *flags); 382 383 #if ARM_PLAT_MT 384 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 385 #endif 386 387 /* 388 * This function is called after loading SCP_BL2 image and it is used to perform 389 * any platform-specific actions required to handle the SCP firmware. 390 */ 391 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 392 393 /* 394 * Optional functions required in ARM standard platforms 395 */ 396 void plat_arm_io_setup(void); 397 int plat_arm_get_alt_image_source( 398 unsigned int image_id, 399 uintptr_t *dev_handle, 400 uintptr_t *image_spec); 401 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 402 const mmap_region_t *plat_arm_get_mmap(void); 403 404 const arm_gpt_info_t *plat_arm_get_gpt_info(void); 405 void arm_gpt_setup(void); 406 407 /* Allow platform to override psci_pm_ops during runtime */ 408 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 409 410 /* Execution state switch in ARM platforms */ 411 int arm_execution_state_switch(unsigned int smc_fid, 412 uint32_t pc_hi, 413 uint32_t pc_lo, 414 uint32_t cookie_hi, 415 uint32_t cookie_lo, 416 void *handle); 417 418 /* Optional functions for SP_MIN */ 419 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 420 u_register_t arg2, u_register_t arg3); 421 422 /* global variables */ 423 extern plat_psci_ops_t plat_arm_psci_pm_ops; 424 extern const mmap_region_t plat_arm_mmap[]; 425 extern const unsigned int arm_pm_idle_states[]; 426 427 /* secure watchdog */ 428 void plat_arm_secure_wdt_start(void); 429 void plat_arm_secure_wdt_stop(void); 430 void plat_arm_secure_wdt_refresh(void); 431 432 /* Get SOC-ID of ARM platform */ 433 uint32_t plat_arm_get_soc_id(void); 434 435 #endif /* PLAT_ARM_H */ 436