1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stddef.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <lib/el3_runtime/context_mgmt.h> 15 #include <lib/el3_runtime/pubsub_events.h> 16 #include <plat/common/platform.h> 17 18 #include "psci_private.h" 19 20 /* 21 * Helper functions for the CPU level spinlocks 22 */ 23 static inline void psci_spin_lock_cpu(unsigned int idx) 24 { 25 spin_lock(&psci_cpu_pd_nodes[idx].cpu_lock); 26 } 27 28 static inline void psci_spin_unlock_cpu(unsigned int idx) 29 { 30 spin_unlock(&psci_cpu_pd_nodes[idx].cpu_lock); 31 } 32 33 /******************************************************************************* 34 * This function checks whether a cpu which has been requested to be turned on 35 * is OFF to begin with. 36 ******************************************************************************/ 37 static int cpu_on_validate_state(aff_info_state_t aff_state) 38 { 39 if (aff_state == AFF_STATE_ON) 40 return PSCI_E_ALREADY_ON; 41 42 if (aff_state == AFF_STATE_ON_PENDING) 43 return PSCI_E_ON_PENDING; 44 45 assert(aff_state == AFF_STATE_OFF); 46 return PSCI_E_SUCCESS; 47 } 48 49 /******************************************************************************* 50 * Generic handler which is called to physically power on a cpu identified by 51 * its mpidr. It performs the generic, architectural, platform setup and state 52 * management to power on the target cpu e.g. it will ensure that 53 * enough information is stashed for it to resume execution in the non-secure 54 * security state. 55 * 56 * The state of all the relevant power domains are changed after calling the 57 * platform handler as it can return error. 58 ******************************************************************************/ 59 int psci_cpu_on_start(u_register_t target_cpu, 60 const entry_point_info_t *ep) 61 { 62 int rc; 63 aff_info_state_t target_aff_state; 64 unsigned int target_idx = (unsigned int)plat_core_pos_by_mpidr(target_cpu); 65 66 /* 67 * This function must only be called on platforms where the 68 * CPU_ON platform hooks have been implemented. 69 */ 70 assert((psci_plat_pm_ops->pwr_domain_on != NULL) && 71 (psci_plat_pm_ops->pwr_domain_on_finish != NULL)); 72 73 /* Protect against multiple CPUs trying to turn ON the same target CPU */ 74 psci_spin_lock_cpu(target_idx); 75 76 /* 77 * Generic management: Ensure that the cpu is off to be 78 * turned on. 79 * Perform cache maintanence ahead of reading the target CPU state to 80 * ensure that the data is not stale. 81 * There is a theoretical edge case where the cache may contain stale 82 * data for the target CPU data - this can occur under the following 83 * conditions: 84 * - the target CPU is in another cluster from the current 85 * - the target CPU was the last CPU to shutdown on its cluster 86 * - the cluster was removed from coherency as part of the CPU shutdown 87 * 88 * In this case the cache maintenace that was performed as part of the 89 * target CPUs shutdown was not seen by the current CPU's cluster. And 90 * so the cache may contain stale data for the target CPU. 91 */ 92 flush_cpu_data_by_index(target_idx, 93 psci_svc_cpu_data.aff_info_state); 94 rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx)); 95 if (rc != PSCI_E_SUCCESS) 96 goto exit; 97 98 /* 99 * Call the cpu on handler registered by the Secure Payload Dispatcher 100 * to let it do any bookeeping. If the handler encounters an error, it's 101 * expected to assert within 102 */ 103 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on != NULL)) 104 psci_spd_pm->svc_on(target_cpu); 105 106 /* 107 * Set the Affinity info state of the target cpu to ON_PENDING. 108 * Flush aff_info_state as it will be accessed with caches 109 * turned OFF. 110 */ 111 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); 112 flush_cpu_data_by_index(target_idx, 113 psci_svc_cpu_data.aff_info_state); 114 115 /* 116 * The cache line invalidation by the target CPU after setting the 117 * state to OFF (see psci_do_cpu_off()), could cause the update to 118 * aff_info_state to be invalidated. Retry the update if the target 119 * CPU aff_info_state is not ON_PENDING. 120 */ 121 target_aff_state = psci_get_aff_info_state_by_idx(target_idx); 122 if (target_aff_state != AFF_STATE_ON_PENDING) { 123 assert(target_aff_state == AFF_STATE_OFF); 124 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); 125 flush_cpu_data_by_index(target_idx, 126 psci_svc_cpu_data.aff_info_state); 127 128 assert(psci_get_aff_info_state_by_idx(target_idx) == 129 AFF_STATE_ON_PENDING); 130 } 131 132 /* 133 * Perform generic, architecture and platform specific handling. 134 */ 135 /* 136 * Plat. management: Give the platform the current state 137 * of the target cpu to allow it to perform the necessary 138 * steps to power on. 139 */ 140 rc = psci_plat_pm_ops->pwr_domain_on(target_cpu); 141 assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL)); 142 143 if (rc == PSCI_E_SUCCESS) 144 /* Store the re-entry information for the non-secure world. */ 145 cm_init_context_by_index(target_idx, ep); 146 else { 147 /* Restore the state on error. */ 148 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF); 149 flush_cpu_data_by_index(target_idx, 150 psci_svc_cpu_data.aff_info_state); 151 } 152 153 exit: 154 psci_spin_unlock_cpu(target_idx); 155 return rc; 156 } 157 158 /******************************************************************************* 159 * The following function finish an earlier power on request. They 160 * are called by the common finisher routine in psci_common.c. The `state_info` 161 * is the psci_power_state from which this CPU has woken up from. 162 ******************************************************************************/ 163 void psci_cpu_on_finish(unsigned int cpu_idx, const psci_power_state_t *state_info) 164 { 165 /* 166 * Plat. management: Perform the platform specific actions 167 * for this cpu e.g. enabling the gic or zeroing the mailbox 168 * register. The actual state of this cpu has already been 169 * changed. 170 */ 171 psci_plat_pm_ops->pwr_domain_on_finish(state_info); 172 173 #if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY) 174 /* 175 * Arch. management: Enable data cache and manage stack memory 176 */ 177 psci_do_pwrup_cache_maintenance(); 178 #endif 179 180 /* 181 * Plat. management: Perform any platform specific actions which 182 * can only be done with the cpu and the cluster guaranteed to 183 * be coherent. 184 */ 185 if (psci_plat_pm_ops->pwr_domain_on_finish_late != NULL) 186 psci_plat_pm_ops->pwr_domain_on_finish_late(state_info); 187 188 /* 189 * All the platform specific actions for turning this cpu 190 * on have completed. Perform enough arch.initialization 191 * to run in the non-secure address space. 192 */ 193 psci_arch_setup(); 194 195 /* 196 * Lock the CPU spin lock to make sure that the context initialization 197 * is done. Since the lock is only used in this function to create 198 * a synchronization point with cpu_on_start(), it can be released 199 * immediately. 200 */ 201 psci_spin_lock_cpu(cpu_idx); 202 psci_spin_unlock_cpu(cpu_idx); 203 204 /* Ensure we have been explicitly woken up by another cpu */ 205 assert(psci_get_aff_info_state() == AFF_STATE_ON_PENDING); 206 207 /* 208 * Call the cpu on finish handler registered by the Secure Payload 209 * Dispatcher to let it do any bookeeping. If the handler encounters an 210 * error, it's expected to assert within 211 */ 212 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on_finish != NULL)) 213 psci_spd_pm->svc_on_finish(0); 214 215 PUBLISH_EVENT(psci_cpu_on_finish); 216 217 /* Populate the mpidr field within the cpu node array */ 218 /* This needs to be done only once */ 219 psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK; 220 } 221