1 /* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/partition/partition.h> 19 #include <lib/fconf/fconf.h> 20 #include <lib/fconf/fconf_dyn_cfg_getter.h> 21 #include <lib/gpt_rme/gpt_rme.h> 22 #ifdef SPD_opteed 23 #include <lib/optee_utils.h> 24 #endif 25 #include <lib/utils.h> 26 #if ENABLE_RME 27 #include <plat/arm/common/arm_pas_def.h> 28 #endif 29 #include <plat/arm/common/plat_arm.h> 30 #include <plat/common/platform.h> 31 32 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 33 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 34 35 /* Base address of fw_config received from BL1 */ 36 static uintptr_t config_base; 37 38 /* 39 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is 40 * for `meminfo_t` data structure and fw_configs passed from BL1. 41 */ 42 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 43 44 /* Weak definitions may be overridden in specific ARM standard platform */ 45 #pragma weak bl2_early_platform_setup2 46 #pragma weak bl2_platform_setup 47 #pragma weak bl2_plat_arch_setup 48 #pragma weak bl2_plat_sec_mem_layout 49 50 #if ENABLE_RME 51 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 52 bl2_tzram_layout.total_base, \ 53 bl2_tzram_layout.total_size, \ 54 MT_MEMORY | MT_RW | MT_ROOT) 55 #else 56 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 57 bl2_tzram_layout.total_base, \ 58 bl2_tzram_layout.total_size, \ 59 MT_MEMORY | MT_RW | MT_SECURE) 60 #endif /* ENABLE_RME */ 61 62 #pragma weak arm_bl2_plat_handle_post_image_load 63 64 /******************************************************************************* 65 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 66 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 67 * Copy it to a safe location before its reclaimed by later BL2 functionality. 68 ******************************************************************************/ 69 void arm_bl2_early_platform_setup(uintptr_t fw_config, 70 struct meminfo *mem_layout) 71 { 72 int __maybe_unused ret; 73 74 /* Initialize the console to provide early debug support */ 75 arm_console_boot_init(); 76 77 /* Setup the BL2 memory layout */ 78 bl2_tzram_layout = *mem_layout; 79 80 config_base = fw_config; 81 82 /* Initialise the IO layer and register platform IO devices */ 83 plat_arm_io_setup(); 84 85 /* Load partition table */ 86 #if ARM_GPT_SUPPORT 87 ret = gpt_partition_init(); 88 if (ret != 0) { 89 ERROR("GPT partition initialisation failed!\n"); 90 panic(); 91 } 92 93 #endif /* ARM_GPT_SUPPORT */ 94 } 95 96 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 97 { 98 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 99 100 generic_delay_timer_init(); 101 } 102 103 /* 104 * Perform BL2 preload setup. Currently we initialise the dynamic 105 * configuration here. 106 */ 107 void bl2_plat_preload_setup(void) 108 { 109 arm_bl2_dyn_cfg_init(); 110 111 #if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT 112 /* Always use the FIP from bank 0 */ 113 arm_set_fip_addr(0U); 114 #endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */ 115 } 116 117 /* 118 * Perform ARM standard platform setup. 119 */ 120 void arm_bl2_platform_setup(void) 121 { 122 #if !ENABLE_RME 123 /* Initialize the secure environment */ 124 plat_arm_security_setup(); 125 #endif 126 127 #if defined(PLAT_ARM_MEM_PROT_ADDR) 128 arm_nor_psci_do_static_mem_protect(); 129 #endif 130 } 131 132 void bl2_platform_setup(void) 133 { 134 arm_bl2_platform_setup(); 135 } 136 137 #if ENABLE_RME 138 static void arm_bl2_plat_gpt_setup(void) 139 { 140 /* 141 * The GPT library might modify the gpt regions structure to optimize 142 * the layout, so the array cannot be constant. 143 */ 144 pas_region_t pas_regions[] = { 145 ARM_PAS_KERNEL, 146 ARM_PAS_SECURE, 147 ARM_PAS_REALM, 148 ARM_PAS_EL3_DRAM, 149 ARM_PAS_GPTS, 150 ARM_PAS_KERNEL_1 151 }; 152 153 /* Initialize entire protected space to GPT_GPI_ANY. */ 154 if (gpt_init_l0_tables(GPCCR_PPS_64GB, ARM_L0_GPT_ADDR_BASE, 155 ARM_L0_GPT_SIZE) < 0) { 156 ERROR("gpt_init_l0_tables() failed!\n"); 157 panic(); 158 } 159 160 /* Carve out defined PAS ranges. */ 161 if (gpt_init_pas_l1_tables(GPCCR_PGS_4K, 162 ARM_L1_GPT_ADDR_BASE, 163 ARM_L1_GPT_SIZE, 164 pas_regions, 165 (unsigned int)(sizeof(pas_regions) / 166 sizeof(pas_region_t))) < 0) { 167 ERROR("gpt_init_pas_l1_tables() failed!\n"); 168 panic(); 169 } 170 171 INFO("Enabling Granule Protection Checks\n"); 172 if (gpt_enable() < 0) { 173 ERROR("gpt_enable() failed!\n"); 174 panic(); 175 } 176 } 177 #endif /* ENABLE_RME */ 178 179 /******************************************************************************* 180 * Perform the very early platform specific architectural setup here. 181 * When RME is enabled the secure environment is initialised before 182 * initialising and enabling Granule Protection. 183 * This function initialises the MMU in a quick and dirty way. 184 ******************************************************************************/ 185 void arm_bl2_plat_arch_setup(void) 186 { 187 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 188 /* 189 * Ensure ARM platforms don't use coherent memory in BL2 unless 190 * cryptocell integration is enabled. 191 */ 192 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 193 #endif 194 195 const mmap_region_t bl_regions[] = { 196 MAP_BL2_TOTAL, 197 ARM_MAP_BL_RO, 198 #if USE_ROMLIB 199 ARM_MAP_ROMLIB_CODE, 200 ARM_MAP_ROMLIB_DATA, 201 #endif 202 #if ARM_CRYPTOCELL_INTEG 203 ARM_MAP_BL_COHERENT_RAM, 204 #endif 205 ARM_MAP_BL_CONFIG_REGION, 206 #if ENABLE_RME 207 ARM_MAP_L0_GPT_REGION, 208 #endif 209 {0} 210 }; 211 212 #if ENABLE_RME 213 /* Initialise the secure environment */ 214 plat_arm_security_setup(); 215 #endif 216 setup_page_tables(bl_regions, plat_arm_get_mmap()); 217 218 #ifdef __aarch64__ 219 #if ENABLE_RME 220 /* BL2 runs in EL3 when RME enabled. */ 221 assert(get_armv9_2_feat_rme_support() != 0U); 222 enable_mmu_el3(0); 223 224 /* Initialise and enable granule protection after MMU. */ 225 arm_bl2_plat_gpt_setup(); 226 #else 227 enable_mmu_el1(0); 228 #endif 229 #else 230 enable_mmu_svc_mon(0); 231 #endif 232 233 arm_setup_romlib(); 234 } 235 236 void bl2_plat_arch_setup(void) 237 { 238 const struct dyn_cfg_dtb_info_t *tb_fw_config_info; 239 240 arm_bl2_plat_arch_setup(); 241 242 /* Fill the properties struct with the info from the config dtb */ 243 fconf_populate("FW_CONFIG", config_base); 244 245 /* TB_FW_CONFIG was also loaded by BL1 */ 246 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID); 247 assert(tb_fw_config_info != NULL); 248 249 fconf_populate("TB_FW", tb_fw_config_info->config_addr); 250 } 251 252 int arm_bl2_handle_post_image_load(unsigned int image_id) 253 { 254 int err = 0; 255 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 256 #ifdef SPD_opteed 257 bl_mem_params_node_t *pager_mem_params = NULL; 258 bl_mem_params_node_t *paged_mem_params = NULL; 259 #endif 260 assert(bl_mem_params != NULL); 261 262 switch (image_id) { 263 #ifdef __aarch64__ 264 case BL32_IMAGE_ID: 265 #ifdef SPD_opteed 266 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 267 assert(pager_mem_params); 268 269 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 270 assert(paged_mem_params); 271 272 err = parse_optee_header(&bl_mem_params->ep_info, 273 &pager_mem_params->image_info, 274 &paged_mem_params->image_info); 275 if (err != 0) { 276 WARN("OPTEE header parse error.\n"); 277 } 278 #endif 279 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 280 break; 281 #endif 282 283 case BL33_IMAGE_ID: 284 /* BL33 expects to receive the primary CPU MPID (through r0) */ 285 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 286 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 287 break; 288 289 #ifdef SCP_BL2_BASE 290 case SCP_BL2_IMAGE_ID: 291 /* The subsequent handling of SCP_BL2 is platform specific */ 292 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 293 if (err) { 294 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 295 } 296 break; 297 #endif 298 default: 299 /* Do nothing in default case */ 300 break; 301 } 302 303 return err; 304 } 305 306 /******************************************************************************* 307 * This function can be used by the platforms to update/use image 308 * information for given `image_id`. 309 ******************************************************************************/ 310 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 311 { 312 #if defined(SPD_spmd) && BL2_ENABLE_SP_LOAD 313 /* For Secure Partitions we don't need post processing */ 314 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && 315 (image_id < MAX_NUMBER_IDS)) { 316 return 0; 317 } 318 #endif 319 return arm_bl2_handle_post_image_load(image_id); 320 } 321