1# 2# Copyright (c) 2016-2023, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture feature modifiers: none by default 23ARM_ARCH_FEATURE := none 24 25# ARM Architecture major and minor versions: 8.0 by default. 26ARM_ARCH_MAJOR := 8 27ARM_ARCH_MINOR := 0 28 29# Base commit to perform code check on 30BASE_COMMIT := origin/master 31 32# Execute BL2 at EL3 33RESET_TO_BL2 := 0 34 35# Only use SP packages if SP layout JSON is defined 36BL2_ENABLE_SP_LOAD := 0 37 38# BL2 image is stored in XIP memory, for now, this option is only supported 39# when RESET_TO_BL2 is 1. 40BL2_IN_XIP_MEM := 0 41 42# Do dcache invalidate upon BL2 entry at EL3 43BL2_INV_DCACHE := 1 44 45# Select the branch protection features to use. 46BRANCH_PROTECTION := 0 47 48# By default, consider that the platform may release several CPUs out of reset. 49# The platform Makefile is free to override this value. 50COLD_BOOT_SINGLE_CPU := 0 51 52# Flag to compile in coreboot support code. Exclude by default. The coreboot 53# Makefile system will set this when compiling TF as part of a coreboot image. 54COREBOOT := 0 55 56# For Chain of Trust 57CREATE_KEYS := 1 58 59# Build flag to include AArch32 registers in cpu context save and restore during 60# world switch. This flag must be set to 0 for AArch64-only platforms. 61CTX_INCLUDE_AARCH32_REGS := 1 62 63# Include FP registers in cpu context 64CTX_INCLUDE_FPREGS := 0 65 66# Debug build 67DEBUG := 0 68 69# By default disable authenticated decryption support. 70DECRYPTION_SUPPORT := none 71 72# Build platform 73DEFAULT_PLAT := fvp 74 75# Disable the generation of the binary image (ELF only). 76DISABLE_BIN_GENERATION := 0 77 78# Enable capability to disable authentication dynamically. Only meant for 79# development platforms. 80DYN_DISABLE_AUTH := 0 81 82# Enable the Maximum Power Mitigation Mechanism on supporting cores. 83ENABLE_MPMM := 0 84 85# Enable MPMM configuration via FCONF. 86ENABLE_MPMM_FCONF := 0 87 88# Flag to Enable Position Independant support (PIE) 89ENABLE_PIE := 0 90 91# Flag to enable Performance Measurement Framework 92ENABLE_PMF := 0 93 94# Flag to enable PSCI STATs functionality 95ENABLE_PSCI_STAT := 0 96 97# Flag to enable runtime instrumentation using PMF 98ENABLE_RUNTIME_INSTRUMENTATION := 0 99 100# Flag to enable stack corruption protection 101ENABLE_STACK_PROTECTOR := 0 102 103# Flag to enable exception handling in EL3 104EL3_EXCEPTION_HANDLING := 0 105 106# By default BL31 encryption disabled 107ENCRYPT_BL31 := 0 108 109# By default BL32 encryption disabled 110ENCRYPT_BL32 := 0 111 112# Default dummy firmware encryption key 113ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 114 115# Default dummy nonce for firmware encryption 116ENC_NONCE := 1234567890abcdef12345678 117 118# Build flag to treat usage of deprecated platform and framework APIs as error. 119ERROR_DEPRECATED := 0 120 121# Fault injection support 122FAULT_INJECTION_SUPPORT := 0 123 124# Flag to enable architectural features detection mechanism 125FEATURE_DETECTION := 0 126 127# Byte alignment that each component in FIP is aligned to 128FIP_ALIGN := 0 129 130# Default FIP file name 131FIP_NAME := fip.bin 132 133# Default FWU_FIP file name 134FWU_FIP_NAME := fwu_fip.bin 135 136# By default firmware encryption with SSK 137FW_ENC_STATUS := 0 138 139# For Chain of Trust 140GENERATE_COT := 0 141 142# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 143# default, they are for Secure EL1. 144GICV2_G0_FOR_EL3 := 0 145 146# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled 147# by lower ELs. 148HANDLE_EA_EL3_FIRST_NS := 0 149 150# Enable Handoff protocol using transfer lists 151TRANSFER_LIST := 0 152 153# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 154# The default value is sha256. 155HASH_ALG := sha256 156 157# Whether system coherency is managed in hardware, without explicit software 158# operations. 159HW_ASSISTED_COHERENCY := 0 160 161# Flag to enable trapping of implementation defined sytem registers 162IMPDEF_SYSREG_TRAP := 0 163 164# Set the default algorithm for the generation of Trusted Board Boot keys 165KEY_ALG := rsa 166 167# Set the default key size in case KEY_ALG is rsa 168ifeq ($(KEY_ALG),rsa) 169KEY_SIZE := 2048 170endif 171 172# Option to build TF with Measured Boot support 173MEASURED_BOOT := 0 174 175# NS timer register save and restore 176NS_TIMER_SWITCH := 0 177 178# Include lib/libc in the final image 179OVERRIDE_LIBC := 0 180 181# Build PL011 UART driver in minimal generic UART mode 182PL011_GENERIC_UART := 0 183 184# By default, consider that the platform's reset address is not programmable. 185# The platform Makefile is free to override this value. 186PROGRAMMABLE_RESET_ADDRESS := 0 187 188# Flag used to choose the power state format: Extended State-ID or Original 189PSCI_EXTENDED_STATE_ID := 0 190 191# Enable PSCI OS-initiated mode support 192PSCI_OS_INIT_MODE := 0 193 194# By default, BL1 acts as the reset handler, not BL31 195RESET_TO_BL31 := 0 196 197# For Chain of Trust 198SAVE_KEYS := 0 199 200# Software Delegated Exception support 201SDEI_SUPPORT := 0 202 203# True Random Number firmware Interface support 204TRNG_SUPPORT := 0 205 206# Check to see if Errata ABI is supported 207ERRATA_ABI_SUPPORT := 0 208 209# Check to enable Errata ABI for platforms with non-arm interconnect 210ERRATA_NON_ARM_INTERCONNECT := 0 211 212# SMCCC PCI support 213SMC_PCI_SUPPORT := 0 214 215# Whether code and read-only data should be put on separate memory pages. The 216# platform Makefile is free to override this value. 217SEPARATE_CODE_AND_RODATA := 0 218 219# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 220# separate memory region, which may be discontiguous from the rest of BL31. 221SEPARATE_NOBITS_REGION := 0 222 223# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory 224# region, platform Makefile is free to override this value. 225SEPARATE_BL2_NOLOAD_REGION := 0 226 227# If the BL31 image initialisation code is recalimed after use for the secondary 228# cores stack 229RECLAIM_INIT_CODE := 0 230 231# SPD choice 232SPD := none 233 234# Enable the Management Mode (MM)-based Secure Partition Manager implementation 235SPM_MM := 0 236 237# Use the FF-A SPMC implementation in EL3. 238SPMC_AT_EL3 := 0 239 240# Enable SEL0 SP when SPMC is enabled at EL3 241SPMC_AT_EL3_SEL0_SP :=0 242 243# Use SPM at S-EL2 as a default config for SPMD 244SPMD_SPM_AT_SEL2 := 1 245 246# Flag to introduce an infinite loop in BL1 just before it exits into the next 247# image. This is meant to help debugging the post-BL2 phase. 248SPIN_ON_BL1_EXIT := 0 249 250# Flags to build TF with Trusted Boot support 251TRUSTED_BOARD_BOOT := 0 252 253# Build option to choose whether Trusted Firmware uses Coherent memory or not. 254USE_COHERENT_MEM := 1 255 256# Build option to add debugfs support 257USE_DEBUGFS := 0 258 259# Build option to fconf based io 260ARM_IO_IN_DTB := 0 261 262# Build option to support SDEI through fconf 263SDEI_IN_FCONF := 0 264 265# Build option to support Secure Interrupt descriptors through fconf 266SEC_INT_DESC_IN_FCONF := 0 267 268# Build option to choose whether Trusted Firmware uses library at ROM 269USE_ROMLIB := 0 270 271# Build option to choose whether the xlat tables of BL images can be read-only. 272# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 273# which is the per BL-image option that actually enables the read-only tables 274# API. The reason for having this additional option is to have a common high 275# level makefile where we can check for incompatible features/build options. 276ALLOW_RO_XLAT_TABLES := 0 277 278# Chain of trust. 279COT := tbbr 280 281# Use tbbr_oid.h instead of platform_oid.h 282USE_TBBR_DEFS := 1 283 284# Build verbosity 285V := 0 286 287# Whether to enable D-Cache early during warm boot. This is usually 288# applicable for platforms wherein interconnect programming is not 289# required to enable cache coherency after warm reset (eg: single cluster 290# platforms). 291WARMBOOT_ENABLE_DCACHE_EARLY := 0 292 293# Default SVE vector length to maximum architected value 294SVE_VECTOR_LEN := 2048 295 296SANITIZE_UB := off 297 298# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 299# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 300# Default: disabled 301USE_SPINLOCK_CAS := 0 302 303# Enable Link Time Optimization 304ENABLE_LTO := 0 305 306# This option will include EL2 registers in cpu context save and restore during 307# EL2 firmware entry/exit. Internal flag not meant for direct setting. 308# Use SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RME=1 to enable 309# CTX_INCLUDE_EL2_REGS. 310CTX_INCLUDE_EL2_REGS := 0 311 312# Enable Memory tag extension which is supported for architecture greater 313# than Armv8.5-A 314# By default it is set to "no" 315SUPPORT_STACK_MEMTAG := no 316 317# Select workaround for AT speculative behaviour. 318ERRATA_SPECULATIVE_AT := 0 319 320# Trap RAS error record access from Non secure 321RAS_TRAP_NS_ERR_REC_ACCESS := 0 322 323# Build option to create cot descriptors using fconf 324COT_DESC_IN_DTB := 0 325 326# Build option to provide OpenSSL directory path 327OPENSSL_DIR := /usr 328 329# Select the openssl binary provided in OPENSSL_DIR variable 330ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "") 331 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps 332else 333 OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin 334endif 335 336# Build option to use the SP804 timer instead of the generic one 337USE_SP804_TIMER := 0 338 339# Build option to define number of firmware banks, used in firmware update 340# metadata structure. 341NR_OF_FW_BANKS := 2 342 343# Build option to define number of images in firmware bank, used in firmware 344# update metadata structure. 345NR_OF_IMAGES_IN_FW_BANK := 1 346 347# Disable Firmware update support by default 348PSA_FWU_SUPPORT := 0 349 350# By default, disable the mocking of RSS provided services 351PLAT_RSS_NOT_SUPPORTED := 0 352 353# Dynamic Root of Trust for Measurement support 354DRTM_SUPPORT := 0 355 356# Check platform if cache management operations should be performed. 357# Disabled by default. 358CONDITIONAL_CMO := 0 359 360# By default, disable SPMD Logical partitions 361ENABLE_SPMD_LP := 0 362 363# By default, disable PSA crypto (use MbedTLS legacy crypto API). 364PSA_CRYPTO := 0 365 366# getc() support from the console(s). 367# Disabled by default because it constitutes an attack vector into TF-A. It 368# should only be enabled if there is a use case for it. 369ENABLE_CONSOLE_GETC := 0 370