1 /* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/arm/common/smccc_def.h> 16 #include <plat/common/common_def.h> 17 18 /****************************************************************************** 19 * Definitions common to all ARM standard platforms 20 *****************************************************************************/ 21 22 /* 23 * Root of trust key lengths 24 */ 25 #define ARM_ROTPK_HEADER_LEN 19 26 #define ARM_ROTPK_HASH_LEN 32 27 28 /* Special value used to verify platform parameters from BL2 to BL31 */ 29 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 30 31 #define ARM_SYSTEM_COUNT U(1) 32 33 #define ARM_CACHE_WRITEBACK_SHIFT 6 34 35 /* 36 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 37 * power levels have a 1:1 mapping with the MPIDR affinity levels. 38 */ 39 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 40 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 41 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 42 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 43 44 /* 45 * Macros for local power states in ARM platforms encoded by State-ID field 46 * within the power-state parameter. 47 */ 48 /* Local power state for power domains in Run state. */ 49 #define ARM_LOCAL_STATE_RUN U(0) 50 /* Local power state for retention. Valid only for CPU power domains */ 51 #define ARM_LOCAL_STATE_RET U(1) 52 /* Local power state for OFF/power-down. Valid for CPU and cluster power 53 domains */ 54 #define ARM_LOCAL_STATE_OFF U(2) 55 56 /* Memory location options for TSP */ 57 #define ARM_TRUSTED_SRAM_ID 0 58 #define ARM_TRUSTED_DRAM_ID 1 59 #define ARM_DRAM_ID 2 60 61 #ifdef PLAT_ARM_TRUSTED_SRAM_BASE 62 #define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE 63 #else 64 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 65 #endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ 66 67 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 68 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 69 70 /* The remaining Trusted SRAM is used to load the BL images */ 71 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 72 ARM_SHARED_RAM_SIZE) 73 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 74 ARM_SHARED_RAM_SIZE) 75 76 /* 77 * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as 78 * follows: 79 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 80 * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled 81 * - REALM DRAM: Reserved for Realm world if RME is enabled 82 * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM 83 * - Event Log: Area for Event Log if MEASURED_BOOT feature is enabled 84 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 85 * 86 * RME enabled(64MB) RME not enabled(16MB) 87 * -------------------- ------------------- 88 * | | | | 89 * | AP TZC (~28MB) | | AP TZC (~14MB) | 90 * -------------------- ------------------- 91 * | Event Log | | Event Log | 92 * | (4KB) | | (4KB) | 93 * -------------------- ------------------- 94 * | REALM (RMM) | | | 95 * | (32MB - 4KB) | | EL3 TZC (2MB) | 96 * -------------------- ------------------- 97 * | | | | 98 * | TF-A <-> RMM | | SCP TZC | 99 * | SHARED (4KB) | 0xFFFF_FFFF------------------- 100 * -------------------- 101 * | | 102 * | EL3 TZC (3MB) | 103 * -------------------- 104 * | L1 GPT + SCP TZC | 105 * | (~1MB) | 106 * 0xFFFF_FFFF -------------------- 107 */ 108 #if ENABLE_RME 109 #define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */ 110 /* 111 * Define a region within the TZC secured DRAM for use by EL3 runtime 112 * firmware. This region is meant to be NOLOAD and will not be zero 113 * initialized. Data sections with the attribute `.arm_el3_tzc_dram` will be 114 * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise. 115 */ 116 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ 117 #define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */ 118 /* 32MB - ARM_EL3_RMM_SHARED_SIZE */ 119 #define ARM_REALM_SIZE (UL(0x02000000) - \ 120 ARM_EL3_RMM_SHARED_SIZE) 121 #define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ 122 #else 123 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */ 124 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */ 125 #define ARM_L1_GPT_SIZE UL(0) 126 #define ARM_REALM_SIZE UL(0) 127 #define ARM_EL3_RMM_SHARED_SIZE UL(0) 128 #endif /* ENABLE_RME */ 129 130 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 131 ARM_DRAM1_SIZE - \ 132 (ARM_SCP_TZC_DRAM1_SIZE + \ 133 ARM_L1_GPT_SIZE)) 134 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 135 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 136 ARM_SCP_TZC_DRAM1_SIZE - 1U) 137 138 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 139 MEASURED_BOOT 140 #define ARM_EVENT_LOG_DRAM1_SIZE UL(0x00001000) /* 4KB */ 141 142 #if ENABLE_RME 143 #define ARM_EVENT_LOG_DRAM1_BASE (ARM_REALM_BASE - \ 144 ARM_EVENT_LOG_DRAM1_SIZE) 145 #else 146 #define ARM_EVENT_LOG_DRAM1_BASE (ARM_EL3_TZC_DRAM1_BASE - \ 147 ARM_EVENT_LOG_DRAM1_SIZE) 148 #endif /* ENABLE_RME */ 149 #define ARM_EVENT_LOG_DRAM1_END (ARM_EVENT_LOG_DRAM1_BASE + \ 150 ARM_EVENT_LOG_DRAM1_SIZE - \ 151 1U) 152 #else 153 #define ARM_EVENT_LOG_DRAM1_SIZE UL(0) 154 #endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ 155 156 #if ENABLE_RME 157 #define ARM_L1_GPT_ADDR_BASE (ARM_DRAM1_BASE + \ 158 ARM_DRAM1_SIZE - \ 159 ARM_L1_GPT_SIZE) 160 #define ARM_L1_GPT_END (ARM_L1_GPT_ADDR_BASE + \ 161 ARM_L1_GPT_SIZE - 1U) 162 163 #define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \ 164 ARM_REALM_SIZE) 165 166 #define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) 167 168 #define ARM_EL3_RMM_SHARED_BASE (ARM_DRAM1_BASE + \ 169 ARM_DRAM1_SIZE - \ 170 (ARM_SCP_TZC_DRAM1_SIZE + \ 171 ARM_L1_GPT_SIZE + \ 172 ARM_EL3_RMM_SHARED_SIZE + \ 173 ARM_EL3_TZC_DRAM1_SIZE)) 174 175 #define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \ 176 ARM_EL3_RMM_SHARED_SIZE - 1U) 177 #endif /* ENABLE_RME */ 178 179 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ 180 ARM_EL3_TZC_DRAM1_SIZE) 181 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 182 ARM_EL3_TZC_DRAM1_SIZE - 1U) 183 184 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 185 ARM_DRAM1_SIZE - \ 186 ARM_TZC_DRAM1_SIZE) 187 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 188 (ARM_SCP_TZC_DRAM1_SIZE + \ 189 ARM_EL3_TZC_DRAM1_SIZE + \ 190 ARM_EL3_RMM_SHARED_SIZE + \ 191 ARM_REALM_SIZE + \ 192 ARM_L1_GPT_SIZE + \ 193 ARM_EVENT_LOG_DRAM1_SIZE)) 194 195 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 196 ARM_AP_TZC_DRAM1_SIZE - 1U) 197 198 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 199 #if ARM_CRYPTOCELL_INTEG 200 /* 201 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 202 * This is required by CryptoCell to authenticate BL33 which is loaded 203 * into the Non Secure DDR. 204 */ 205 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 206 #else 207 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 208 #endif 209 210 #ifdef SPD_opteed 211 /* 212 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 213 * load/authenticate the trusted os extra image. The first 512KB of 214 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 215 * for OPTEE is paged image which only include the paging part using 216 * virtual memory but without "init" data. OPTEE will copy the "init" data 217 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 218 * extra image behind the "init" data. 219 */ 220 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 221 ARM_AP_TZC_DRAM1_SIZE - \ 222 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 223 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 224 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 225 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 226 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 227 MT_MEMORY | MT_RW | MT_SECURE) 228 229 /* 230 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 231 * support is enabled). 232 */ 233 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 234 BL32_BASE, \ 235 BL32_LIMIT - BL32_BASE, \ 236 MT_MEMORY | MT_RW | MT_SECURE) 237 #endif /* SPD_opteed */ 238 239 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 240 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 241 ARM_TZC_DRAM1_SIZE) 242 243 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 244 ARM_NS_DRAM1_SIZE - 1U) 245 #ifdef PLAT_ARM_DRAM1_BASE 246 #define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE 247 #else 248 #define ARM_DRAM1_BASE ULL(0x80000000) 249 #endif /* PLAT_ARM_DRAM1_BASE */ 250 251 #define ARM_DRAM1_SIZE ULL(0x80000000) 252 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 253 ARM_DRAM1_SIZE - 1U) 254 255 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 256 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 257 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 258 ARM_DRAM2_SIZE - 1U) 259 /* Number of DRAM banks */ 260 #define ARM_DRAM_NUM_BANKS 2UL 261 262 #define ARM_IRQ_SEC_PHY_TIMER 29 263 264 #define ARM_IRQ_SEC_SGI_0 8 265 #define ARM_IRQ_SEC_SGI_1 9 266 #define ARM_IRQ_SEC_SGI_2 10 267 #define ARM_IRQ_SEC_SGI_3 11 268 #define ARM_IRQ_SEC_SGI_4 12 269 #define ARM_IRQ_SEC_SGI_5 13 270 #define ARM_IRQ_SEC_SGI_6 14 271 #define ARM_IRQ_SEC_SGI_7 15 272 273 /* 274 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 275 * terminology. On a GICv2 system or mode, the lists will be merged and treated 276 * as Group 0 interrupts. 277 */ 278 #define ARM_G1S_IRQ_PROPS(grp) \ 279 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 280 GIC_INTR_CFG_LEVEL), \ 281 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 282 GIC_INTR_CFG_EDGE), \ 283 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 284 GIC_INTR_CFG_EDGE), \ 285 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 286 GIC_INTR_CFG_EDGE), \ 287 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 288 GIC_INTR_CFG_EDGE), \ 289 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 290 GIC_INTR_CFG_EDGE), \ 291 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 292 GIC_INTR_CFG_EDGE) 293 294 #define ARM_G0_IRQ_PROPS(grp) \ 295 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 296 GIC_INTR_CFG_EDGE), \ 297 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 298 GIC_INTR_CFG_EDGE) 299 300 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 301 ARM_SHARED_RAM_BASE, \ 302 ARM_SHARED_RAM_SIZE, \ 303 MT_DEVICE | MT_RW | EL3_PAS) 304 305 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 306 ARM_NS_DRAM1_BASE, \ 307 ARM_NS_DRAM1_SIZE, \ 308 MT_MEMORY | MT_RW | MT_NS) 309 310 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 311 ARM_DRAM2_BASE, \ 312 ARM_DRAM2_SIZE, \ 313 MT_MEMORY | MT_RW | MT_NS) 314 315 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 316 TSP_SEC_MEM_BASE, \ 317 TSP_SEC_MEM_SIZE, \ 318 MT_MEMORY | MT_RW | MT_SECURE) 319 320 #if ARM_BL31_IN_DRAM 321 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 322 BL31_BASE, \ 323 PLAT_ARM_MAX_BL31_SIZE, \ 324 MT_MEMORY | MT_RW | MT_SECURE) 325 #endif 326 327 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 328 ARM_EL3_TZC_DRAM1_BASE, \ 329 ARM_EL3_TZC_DRAM1_SIZE, \ 330 MT_MEMORY | MT_RW | EL3_PAS) 331 332 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 333 PLAT_ARM_TRUSTED_DRAM_BASE, \ 334 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 335 MT_MEMORY | MT_RW | MT_SECURE) 336 337 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 338 MEASURED_BOOT 339 #define ARM_MAP_EVENT_LOG_DRAM1 \ 340 MAP_REGION_FLAT( \ 341 ARM_EVENT_LOG_DRAM1_BASE, \ 342 ARM_EVENT_LOG_DRAM1_SIZE, \ 343 MT_MEMORY | MT_RW | MT_SECURE) 344 #endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ 345 346 #if ENABLE_RME 347 /* 348 * We add the EL3_RMM_SHARED size to RMM mapping to map the region as a block. 349 * Else we end up requiring more pagetables in BL2 for ROMLIB build. 350 */ 351 #define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \ 352 PLAT_ARM_RMM_BASE, \ 353 (PLAT_ARM_RMM_SIZE + \ 354 ARM_EL3_RMM_SHARED_SIZE), \ 355 MT_MEMORY | MT_RW | MT_REALM) 356 357 358 #define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \ 359 ARM_L1_GPT_ADDR_BASE, \ 360 ARM_L1_GPT_SIZE, \ 361 MT_MEMORY | MT_RW | EL3_PAS) 362 363 #define ARM_MAP_EL3_RMM_SHARED_MEM \ 364 MAP_REGION_FLAT( \ 365 ARM_EL3_RMM_SHARED_BASE, \ 366 ARM_EL3_RMM_SHARED_SIZE, \ 367 MT_MEMORY | MT_RW | MT_REALM) 368 369 #endif /* ENABLE_RME */ 370 371 /* 372 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 373 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 374 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 375 * to be able to access the heap. 376 */ 377 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 378 BL1_RW_BASE, \ 379 BL1_RW_LIMIT - BL1_RW_BASE, \ 380 MT_MEMORY | MT_RW | EL3_PAS) 381 382 /* 383 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 384 * otherwise one region is defined containing both. 385 */ 386 #if SEPARATE_CODE_AND_RODATA 387 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 388 BL_CODE_BASE, \ 389 BL_CODE_END - BL_CODE_BASE, \ 390 MT_CODE | EL3_PAS), \ 391 MAP_REGION_FLAT( \ 392 BL_RO_DATA_BASE, \ 393 BL_RO_DATA_END \ 394 - BL_RO_DATA_BASE, \ 395 MT_RO_DATA | EL3_PAS) 396 #else 397 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 398 BL_CODE_BASE, \ 399 BL_CODE_END - BL_CODE_BASE, \ 400 MT_CODE | EL3_PAS) 401 #endif 402 #if USE_COHERENT_MEM 403 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 404 BL_COHERENT_RAM_BASE, \ 405 BL_COHERENT_RAM_END \ 406 - BL_COHERENT_RAM_BASE, \ 407 MT_DEVICE | MT_RW | EL3_PAS) 408 #endif 409 #if USE_ROMLIB 410 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 411 ROMLIB_RO_BASE, \ 412 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 413 MT_CODE | EL3_PAS) 414 415 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 416 ROMLIB_RW_BASE, \ 417 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 418 MT_MEMORY | MT_RW | EL3_PAS) 419 #endif 420 421 /* 422 * Map mem_protect flash region with read and write permissions 423 */ 424 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 425 V2M_FLASH_BLOCK_SIZE, \ 426 MT_DEVICE | MT_RW | MT_SECURE) 427 /* 428 * Map the region for device tree configuration with read and write permissions 429 */ 430 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ 431 (ARM_FW_CONFIGS_LIMIT \ 432 - ARM_BL_RAM_BASE), \ 433 MT_MEMORY | MT_RW | EL3_PAS) 434 /* 435 * Map L0_GPT with read and write permissions 436 */ 437 #if ENABLE_RME 438 #define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_ADDR_BASE, \ 439 ARM_L0_GPT_SIZE, \ 440 MT_MEMORY | MT_RW | MT_ROOT) 441 #endif 442 443 /* 444 * The max number of regions like RO(code), coherent and data required by 445 * different BL stages which need to be mapped in the MMU. 446 */ 447 #define ARM_BL_REGIONS 7 448 449 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 450 ARM_BL_REGIONS) 451 452 /* Memory mapped Generic timer interfaces */ 453 #ifdef PLAT_ARM_SYS_CNTCTL_BASE 454 #define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE 455 #else 456 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 457 #endif 458 459 #ifdef PLAT_ARM_SYS_CNTREAD_BASE 460 #define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE 461 #else 462 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 463 #endif 464 465 #ifdef PLAT_ARM_SYS_TIMCTL_BASE 466 #define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE 467 #else 468 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 469 #endif 470 471 #ifdef PLAT_ARM_SYS_CNT_BASE_S 472 #define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S 473 #else 474 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 475 #endif 476 477 #ifdef PLAT_ARM_SYS_CNT_BASE_NS 478 #define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS 479 #else 480 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 481 #endif 482 483 #define ARM_CONSOLE_BAUDRATE 115200 484 485 /* Trusted Watchdog constants */ 486 #ifdef PLAT_ARM_SP805_TWDG_BASE 487 #define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE 488 #else 489 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 490 #endif 491 #define ARM_SP805_TWDG_CLK_HZ 32768 492 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 493 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 494 #define ARM_TWDG_TIMEOUT_SEC 128 495 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 496 ARM_TWDG_TIMEOUT_SEC) 497 498 /****************************************************************************** 499 * Required platform porting definitions common to all ARM standard platforms 500 *****************************************************************************/ 501 502 /* 503 * This macro defines the deepest retention state possible. A higher state 504 * id will represent an invalid or a power down state. 505 */ 506 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 507 508 /* 509 * This macro defines the deepest power down states possible. Any state ID 510 * higher than this is invalid. 511 */ 512 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 513 514 /* 515 * Some data must be aligned on the biggest cache line size in the platform. 516 * This is known only to the platform as it might have a combination of 517 * integrated and external caches. 518 */ 519 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 520 521 /* 522 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 523 * and limit. Leave enough space of BL2 meminfo. 524 */ 525 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 526 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 527 + (PAGE_SIZE / 2U)) 528 529 /* 530 * Boot parameters passed from BL2 to BL31/BL32 are stored here 531 */ 532 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 533 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 534 + (PAGE_SIZE / 2U)) 535 536 /* 537 * Define limit of firmware configuration memory: 538 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 539 */ 540 #define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2) 541 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE) 542 543 #if ENABLE_RME 544 /* 545 * Store the L0 GPT on Trusted SRAM next to firmware 546 * configuration memory, 4KB aligned. 547 */ 548 #define ARM_L0_GPT_SIZE (PAGE_SIZE) 549 #define ARM_L0_GPT_ADDR_BASE (ARM_FW_CONFIGS_LIMIT) 550 #define ARM_L0_GPT_LIMIT (ARM_L0_GPT_ADDR_BASE + ARM_L0_GPT_SIZE) 551 #else 552 #define ARM_L0_GPT_SIZE U(0) 553 #endif 554 555 /******************************************************************************* 556 * BL1 specific defines. 557 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 558 * addresses. 559 ******************************************************************************/ 560 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 561 #ifdef PLAT_BL1_RO_LIMIT 562 #define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT 563 #else 564 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 565 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 566 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 567 #endif 568 569 /* 570 * Put BL1 RW at the top of the Trusted SRAM. 571 */ 572 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 573 ARM_BL_RAM_SIZE - \ 574 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 575 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 576 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 577 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 578 579 #define ROMLIB_RO_BASE BL1_RO_LIMIT 580 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 581 582 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 583 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 584 585 /******************************************************************************* 586 * BL2 specific defines. 587 ******************************************************************************/ 588 #if RESET_TO_BL2 589 #if ENABLE_PIE 590 /* 591 * As the BL31 image size appears to be increased when built with the ENABLE_PIE 592 * option, set BL2 base address to have enough space for BL31 in Trusted SRAM. 593 */ 594 #define BL2_OFFSET (0x5000) 595 #else 596 /* Put BL2 towards the middle of the Trusted SRAM */ 597 #define BL2_OFFSET (0x2000) 598 #endif /* ENABLE_PIE */ 599 600 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 601 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ 602 BL2_OFFSET) 603 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 604 605 #else 606 /* 607 * Put BL2 just below BL1. 608 */ 609 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 610 #define BL2_LIMIT BL1_RW_BASE 611 #endif 612 613 /******************************************************************************* 614 * BL31 specific defines. 615 ******************************************************************************/ 616 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 617 /* 618 * Put BL31 at the bottom of TZC secured DRAM 619 */ 620 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 621 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 622 PLAT_ARM_MAX_BL31_SIZE) 623 /* 624 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 625 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 626 */ 627 #if SEPARATE_NOBITS_REGION 628 #define BL31_NOBITS_BASE BL2_BASE 629 #define BL31_NOBITS_LIMIT BL2_LIMIT 630 #endif /* SEPARATE_NOBITS_REGION */ 631 #elif (RESET_TO_BL31) 632 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 633 # if !ENABLE_PIE 634 # error "BL31 must be a PIE if RESET_TO_BL31=1." 635 #endif 636 /* 637 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 638 * used for building BL31 and not used for loading BL31. 639 */ 640 # define BL31_BASE 0x0 641 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 642 #else 643 /* Put BL31 below BL2 in the Trusted SRAM.*/ 644 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 645 - PLAT_ARM_MAX_BL31_SIZE) 646 #define BL31_PROGBITS_LIMIT BL2_BASE 647 /* 648 * For RESET_TO_BL2 make sure the BL31 can grow up until BL2_BASE. 649 * This is because in the RESET_TO_BL2 configuration, 650 * BL2 is always resident. 651 */ 652 #if RESET_TO_BL2 653 #define BL31_LIMIT BL2_BASE 654 #else 655 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 656 #endif 657 #endif 658 659 /****************************************************************************** 660 * RMM specific defines 661 *****************************************************************************/ 662 #if ENABLE_RME 663 #define RMM_BASE (ARM_REALM_BASE) 664 #define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) 665 #define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) 666 #define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) 667 #endif 668 669 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 670 /******************************************************************************* 671 * BL32 specific defines for EL3 runtime in AArch32 mode 672 ******************************************************************************/ 673 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 674 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 675 # if !ENABLE_PIE 676 # error "BL32 must be a PIE if RESET_TO_SP_MIN=1." 677 #endif 678 /* 679 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely 680 * used for building BL32 and not used for loading BL32. 681 */ 682 # define BL32_BASE 0x0 683 # define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE 684 # else 685 /* Put BL32 below BL2 in the Trusted SRAM.*/ 686 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 687 - PLAT_ARM_MAX_BL32_SIZE) 688 # define BL32_PROGBITS_LIMIT BL2_BASE 689 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 690 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 691 692 #else 693 /******************************************************************************* 694 * BL32 specific defines for EL3 runtime in AArch64 mode 695 ******************************************************************************/ 696 /* 697 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 698 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 699 * controller. 700 */ 701 # if SPM_MM || SPMC_AT_EL3 702 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 703 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 704 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 705 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 706 ARM_AP_TZC_DRAM1_SIZE) 707 # elif defined(SPD_spmd) 708 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 709 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 710 # define BL32_BASE PLAT_ARM_SPMC_BASE 711 # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ 712 PLAT_ARM_SPMC_SIZE) 713 # elif ARM_BL31_IN_DRAM 714 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 715 PLAT_ARM_MAX_BL31_SIZE) 716 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 717 PLAT_ARM_MAX_BL31_SIZE) 718 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 719 PLAT_ARM_MAX_BL31_SIZE) 720 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 721 ARM_AP_TZC_DRAM1_SIZE) 722 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 723 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 724 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 725 # define TSP_PROGBITS_LIMIT BL31_BASE 726 # define BL32_BASE ARM_FW_CONFIGS_LIMIT 727 # define BL32_LIMIT BL31_BASE 728 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 729 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 730 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 731 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 732 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 733 + SZ_4M) 734 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 735 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 736 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 737 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 738 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 739 ARM_AP_TZC_DRAM1_SIZE) 740 # else 741 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 742 # endif 743 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 744 745 /* 746 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 747 * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be 748 * used as BL32. 749 */ 750 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 751 # if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3 752 # undef BL32_BASE 753 # endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */ 754 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 755 756 /******************************************************************************* 757 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 758 ******************************************************************************/ 759 #define BL2U_BASE BL2_BASE 760 #define BL2U_LIMIT BL2_LIMIT 761 762 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 763 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 764 765 /* 766 * ID of the secure physical generic timer interrupt used by the TSP. 767 */ 768 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 769 770 771 /* 772 * One cache line needed for bakery locks on ARM platforms 773 */ 774 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 775 776 /* Priority levels for ARM platforms */ 777 #if ENABLE_FEAT_RAS && FFH_SUPPORT 778 #define PLAT_RAS_PRI 0x10 779 #endif 780 #define PLAT_SDEI_CRITICAL_PRI 0x60 781 #define PLAT_SDEI_NORMAL_PRI 0x70 782 783 /* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */ 784 #define PLAT_CORE_FAULT_IRQ 17 785 786 /* ARM platforms use 3 upper bits of secure interrupt priority */ 787 #define PLAT_PRI_BITS 3 788 789 /* SGI used for SDEI signalling */ 790 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 791 792 #if SDEI_IN_FCONF 793 /* ARM SDEI dynamic private event max count */ 794 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 795 796 /* ARM SDEI dynamic shared event max count */ 797 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 798 #else 799 /* ARM SDEI dynamic private event numbers */ 800 #define ARM_SDEI_DP_EVENT_0 1000 801 #define ARM_SDEI_DP_EVENT_1 1001 802 #define ARM_SDEI_DP_EVENT_2 1002 803 804 /* ARM SDEI dynamic shared event numbers */ 805 #define ARM_SDEI_DS_EVENT_0 2000 806 #define ARM_SDEI_DS_EVENT_1 2001 807 #define ARM_SDEI_DS_EVENT_2 2002 808 809 #define ARM_SDEI_PRIVATE_EVENTS \ 810 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 811 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 812 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 813 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 814 815 #define ARM_SDEI_SHARED_EVENTS \ 816 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 817 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 818 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 819 #endif /* SDEI_IN_FCONF */ 820 821 #endif /* ARM_DEF_H */ 822