1# 2# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25FVP_DT_PREFIX := fvp-base-gicv3-psci 26 27# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 28# the FVP platform. This option defaults to 256. 29FVP_TRUSTED_SRAM_SIZE := 256 30 31# Macro to enable helpers for running SPM tests. Disabled by default. 32PLAT_TEST_SPM := 0 33 34# This is a very trickly TEMPORARY fix. Enabling ALL features exceeds BL31's 35# progbits limit. We need a way to build all useful configurations while waiting 36# on the fvp to increase its SRAM size. The problem is twofild: 37# 1. the cleanup that introduced these enables cleaned up tf-a a little too 38# well and things that previously (incorrectly) were enabled, no longer are. 39# A bunch of CI configs build subtly incorrectly and this combo makes it 40# necessary to forcefully and unconditionally enable them here. 41# 2. the progbits limit is exceeded only when the tsp is involved. However, 42# there are tsp CI configs that run on very high architecture revisions so 43# disabling everything isn't an option. 44# The fix is to enable everything, as before. When the tsp is included, though, 45# we need to slim the size down. In that case, disable all optional features, 46# that will not be present in CI when the tsp is. 47# Similarly, DRTM support is only tested on v8.0 models. Disable everything just 48# for it. 49# TODO: make all of this unconditional (or only base the condition on 50# ARM_ARCH_* when the makefile supports it). 51ifneq (${DRTM_SUPPORT}, 1) 52ifneq (${SPD}, tspd) 53 ENABLE_FEAT_AMU := 2 54 ENABLE_FEAT_AMUv1p1 := 2 55 ENABLE_FEAT_HCX := 2 56 ENABLE_FEAT_RNG := 2 57 ENABLE_FEAT_TWED := 2 58 ENABLE_FEAT_GCS := 2 59ifeq (${ARCH}, aarch64) 60ifeq (${SPM_MM}, 0) 61ifeq (${CTX_INCLUDE_FPREGS}, 0) 62 ENABLE_SME_FOR_NS := 2 63 ENABLE_SME2_FOR_NS := 2 64endif 65endif 66endif 67endif 68 69# enable unconditionally for all builds 70ifeq (${ARCH}, aarch64) 71 ENABLE_BRBE_FOR_NS := 2 72 ENABLE_TRBE_FOR_NS := 2 73endif 74ENABLE_SYS_REG_TRACE_FOR_NS := 2 75ENABLE_FEAT_CSV2_2 := 2 76ENABLE_FEAT_CSV2_3 := 2 77ENABLE_FEAT_DIT := 2 78ENABLE_FEAT_PAN := 2 79ENABLE_FEAT_VHE := 2 80CTX_INCLUDE_NEVE_REGS := 2 81ENABLE_FEAT_SEL2 := 2 82ENABLE_TRF_FOR_NS := 2 83ENABLE_FEAT_ECV := 2 84ENABLE_FEAT_FGT := 2 85ENABLE_FEAT_TCR2 := 2 86ENABLE_FEAT_S2PIE := 2 87ENABLE_FEAT_S1PIE := 2 88ENABLE_FEAT_S2POE := 2 89ENABLE_FEAT_S1POE := 2 90endif 91 92# The FVP platform depends on this macro to build with correct GIC driver. 93$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 94 95# Pass FVP_CLUSTER_COUNT to the build system. 96$(eval $(call add_define,FVP_CLUSTER_COUNT)) 97 98# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 99$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 100 101# Pass FVP_MAX_PE_PER_CPU to the build system. 102$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 103 104# Pass FVP_GICR_REGION_PROTECTION to the build system. 105$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 106 107# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 108$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 109 110# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 111# choose the CCI driver , else the CCN driver 112ifeq ($(FVP_CLUSTER_COUNT), 0) 113$(error "Incorrect cluster count specified for FVP port") 114else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 115FVP_INTERCONNECT_DRIVER := FVP_CCI 116else 117FVP_INTERCONNECT_DRIVER := FVP_CCN 118endif 119 120$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 121 122# Choose the GIC sources depending upon the how the FVP will be invoked 123ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 124 125# The GIC model (GIC-600 or GIC-500) will be detected at runtime 126GICV3_SUPPORT_GIC600 := 1 127GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 128 129# Include GICv3 driver files 130include drivers/arm/gic/v3/gicv3.mk 131 132FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 133 plat/common/plat_gicv3.c \ 134 plat/arm/common/arm_gicv3.c 135 136 ifeq ($(filter 1,${RESET_TO_BL2} \ 137 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 138 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 139 endif 140 141else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 142 143# No GICv4 extension 144GIC_ENABLE_V4_EXTN := 0 145$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 146 147# Include GICv2 driver files 148include drivers/arm/gic/v2/gicv2.mk 149 150FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 151 plat/common/plat_gicv2.c \ 152 plat/arm/common/arm_gicv2.c 153 154FVP_DT_PREFIX := fvp-base-gicv2-psci 155else 156$(error "Incorrect GIC driver chosen on FVP port") 157endif 158 159ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 160FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 161else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 162FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 163 plat/arm/common/arm_ccn.c 164else 165$(error "Incorrect CCN driver chosen on FVP port") 166endif 167 168FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 169 plat/arm/board/fvp/fvp_security.c \ 170 plat/arm/common/arm_tzc400.c 171 172 173PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 174 -Iinclude/lib/psa 175 176 177PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 178 179FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 180 181ifeq (${ARCH}, aarch64) 182 183# select a different set of CPU files, depending on whether we compile for 184# hardware assisted coherency cores or not 185ifeq (${HW_ASSISTED_COHERENCY}, 0) 186# Cores used without DSU 187 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 188 lib/cpus/aarch64/cortex_a53.S \ 189 lib/cpus/aarch64/cortex_a57.S \ 190 lib/cpus/aarch64/cortex_a72.S \ 191 lib/cpus/aarch64/cortex_a73.S 192else 193# Cores used with DSU only 194 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 195 # AArch64-only cores 196 # TODO: add all cores to the appropriate lists 197 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 198 lib/cpus/aarch64/cortex_a65ae.S \ 199 lib/cpus/aarch64/cortex_a76.S \ 200 lib/cpus/aarch64/cortex_a76ae.S \ 201 lib/cpus/aarch64/cortex_a77.S \ 202 lib/cpus/aarch64/cortex_a78.S \ 203 lib/cpus/aarch64/cortex_a78_ae.S \ 204 lib/cpus/aarch64/cortex_a78c.S \ 205 lib/cpus/aarch64/cortex_a710.S \ 206 lib/cpus/aarch64/cortex_a715.S \ 207 lib/cpus/aarch64/cortex_a720.S \ 208 lib/cpus/aarch64/neoverse_n_common.S \ 209 lib/cpus/aarch64/neoverse_n1.S \ 210 lib/cpus/aarch64/neoverse_n2.S \ 211 lib/cpus/aarch64/neoverse_v1.S \ 212 lib/cpus/aarch64/neoverse_e1.S \ 213 lib/cpus/aarch64/cortex_x2.S \ 214 lib/cpus/aarch64/cortex_x4.S \ 215 lib/cpus/aarch64/cortex_gelas.S \ 216 lib/cpus/aarch64/nevis.S \ 217 lib/cpus/aarch64/travis.S 218 endif 219 # AArch64/AArch32 cores 220 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 221 lib/cpus/aarch64/cortex_a75.S 222endif 223 224else 225FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 226 lib/cpus/aarch32/cortex_a57.S \ 227 lib/cpus/aarch32/cortex_a53.S 228endif 229 230BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 231 drivers/arm/sp805/sp805.c \ 232 drivers/delay_timer/delay_timer.c \ 233 drivers/io/io_semihosting.c \ 234 lib/semihosting/semihosting.c \ 235 lib/semihosting/${ARCH}/semihosting_call.S \ 236 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 237 plat/arm/board/fvp/fvp_bl1_setup.c \ 238 plat/arm/board/fvp/fvp_err.c \ 239 plat/arm/board/fvp/fvp_io_storage.c \ 240 plat/arm/board/fvp/fvp_topology.c \ 241 ${FVP_CPU_LIBS} \ 242 ${FVP_INTERCONNECT_SOURCES} 243 244ifeq (${USE_SP804_TIMER},1) 245BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 246else 247BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 248endif 249 250 251BL2_SOURCES += drivers/arm/sp805/sp805.c \ 252 drivers/io/io_semihosting.c \ 253 lib/utils/mem_region.c \ 254 lib/semihosting/semihosting.c \ 255 lib/semihosting/${ARCH}/semihosting_call.S \ 256 plat/arm/board/fvp/fvp_bl2_setup.c \ 257 plat/arm/board/fvp/fvp_err.c \ 258 plat/arm/board/fvp/fvp_io_storage.c \ 259 plat/arm/common/arm_nor_psci_mem_protect.c \ 260 ${FVP_SECURITY_SOURCES} 261 262 263ifeq (${COT_DESC_IN_DTB},1) 264BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 265endif 266 267ifeq (${ENABLE_RME},1) 268BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S 269 270BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 271 plat/arm/board/fvp/fvp_realm_attest_key.c 272endif 273 274ifeq (${ENABLE_FEAT_RNG_TRAP},1) 275BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 276endif 277 278ifeq (${RESET_TO_BL2},1) 279BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 280 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 281 ${FVP_CPU_LIBS} \ 282 ${FVP_INTERCONNECT_SOURCES} 283endif 284 285ifeq (${USE_SP804_TIMER},1) 286BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 287endif 288 289BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 290 ${FVP_SECURITY_SOURCES} 291 292ifeq (${USE_SP804_TIMER},1) 293BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 294endif 295 296BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 297 drivers/arm/smmu/smmu_v3.c \ 298 drivers/delay_timer/delay_timer.c \ 299 drivers/cfi/v2m/v2m_flash.c \ 300 lib/utils/mem_region.c \ 301 plat/arm/board/fvp/fvp_bl31_setup.c \ 302 plat/arm/board/fvp/fvp_console.c \ 303 plat/arm/board/fvp/fvp_pm.c \ 304 plat/arm/board/fvp/fvp_topology.c \ 305 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 306 plat/arm/common/arm_nor_psci_mem_protect.c \ 307 ${FVP_CPU_LIBS} \ 308 ${FVP_GIC_SOURCES} \ 309 ${FVP_INTERCONNECT_SOURCES} \ 310 ${FVP_SECURITY_SOURCES} 311 312# Support for fconf in BL31 313# Added separately from the above list for better readability 314ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 315BL31_SOURCES += lib/fconf/fconf.c \ 316 lib/fconf/fconf_dyn_cfg_getter.c \ 317 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 318 319BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 320 321ifeq (${SEC_INT_DESC_IN_FCONF},1) 322BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 323endif 324 325endif 326 327ifeq (${USE_SP804_TIMER},1) 328BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 329else 330BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 331endif 332 333ifeq (${TRANSFER_LIST}, 1) 334include lib/transfer_list/transfer_list.mk 335endif 336 337# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 338ifdef UNIX_MK 339FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 340FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 341 342FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 343$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 344 345ifeq (${TRANSFER_LIST}, 1) 346FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 347 ${PLAT}_tb_fw_config.dts \ 348 ) 349else 350FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 351 ${PLAT}_fw_config.dts \ 352 ${PLAT}_tb_fw_config.dts \ 353 ${PLAT}_soc_fw_config.dts \ 354 ${PLAT}_nt_fw_config.dts \ 355 ) 356 357FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 358FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 359FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 360 361ifeq (${SPD},tspd) 362FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 363FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 364 365# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 366$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 367endif 368 369ifeq (${SPD},spmd) 370 371ifeq ($(ARM_SPMC_MANIFEST_DTS),) 372ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 373endif 374 375FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 376FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 377 378# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 379$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 380endif 381 382# Add the FW_CONFIG to FIP and specify the same to certtool 383$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 384# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 385$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 386# Add the NT_FW_CONFIG to FIP and specify the same to certtool 387$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 388endif 389 390# Add the TB_FW_CONFIG to FIP and specify the same to certtool 391$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 392# Add the HW_CONFIG to FIP and specify the same to certtool 393$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 394endif 395 396# Enable dynamic mitigation support by default 397DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 398 399ifneq (${ENABLE_FEAT_AMU},0) 400BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 401 lib/cpus/aarch64/cpuamu_helpers.S 402 403ifeq (${HW_ASSISTED_COHERENCY}, 1) 404BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 405 lib/cpus/aarch64/neoverse_n1_pubsub.c 406endif 407endif 408 409ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 410 ifeq (${ENABLE_FEAT_RAS},1) 411 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 412 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 413 else 414 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 415 endif 416 else 417 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 418 endif 419endif 420 421ifneq (${ENABLE_STACK_PROTECTOR},0) 422PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 423endif 424 425# Enable the dynamic translation tables library. 426ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 427 ifeq (${ARCH},aarch32) 428 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 429 else # AArch64 430 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 431 endif 432endif 433 434ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 435 ifeq (${ARCH},aarch32) 436 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 437 else # AArch64 438 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 439 ifeq (${SPD},tspd) 440 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 441 endif 442 endif 443endif 444 445ifeq (${USE_DEBUGFS},1) 446 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 447endif 448 449# Add support for platform supplied linker script for BL31 build 450$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 451 452ifneq (${RESET_TO_BL2}, 0) 453 override BL1_SOURCES = 454endif 455 456include plat/arm/board/common/board_common.mk 457include plat/arm/common/arm_common.mk 458 459ifeq (${MEASURED_BOOT},1) 460BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 461 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 462 lib/psa/measured_boot.c 463 464BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 465 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 466 lib/psa/measured_boot.c 467endif 468 469ifeq (${DRTM_SUPPORT}, 1) 470BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 471 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 472 plat/arm/board/fvp/fvp_drtm_err.c \ 473 plat/arm/board/fvp/fvp_drtm_measurement.c \ 474 plat/arm/board/fvp/fvp_drtm_stub.c \ 475 plat/arm/common/arm_dyn_cfg.c \ 476 plat/arm/board/fvp/fvp_err.c 477endif 478 479ifeq (${TRUSTED_BOARD_BOOT}, 1) 480BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 481BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 482 483# FVP being a development platform, enable capability to disable Authentication 484# dynamically if TRUSTED_BOARD_BOOT is set. 485DYN_DISABLE_AUTH := 1 486endif 487 488ifeq (${SPMC_AT_EL3}, 1) 489PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 490endif 491 492PSCI_OS_INIT_MODE := 1 493 494ifeq (${SPD},spmd) 495BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 496endif 497 498# Test specific macros, keep them at bottom of this file 499$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 500ifeq (${PLATFORM_TEST_EA_FFH}, 1) 501 ifeq (${FFH_SUPPORT}, 0) 502 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 503 endif 504 505endif 506 507$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 508ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 509 ifeq (${ENABLE_FEAT_RAS}, 0) 510 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 511 endif 512 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 513 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 514 endif 515endif 516 517$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 518ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 519 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 520 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 521 endif 522 ifeq (${ENABLE_SPMD_LP}, 0) 523 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 524 endif 525 ifeq (${ENABLE_FEAT_RAS}, 0) 526 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 527 endif 528 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 529 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 530 endif 531endif 532 533ifeq (${ERRATA_ABI_SUPPORT}, 1) 534include plat/arm/board/fvp/fvp_cpu_errata.mk 535endif 536 537# Build macro necessary for running SPM tests on FVP platform 538$(eval $(call add_define,PLAT_TEST_SPM)) 539