1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 49 SP nodes in tb_fw_config. 50 51- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 52 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 53 54- ``BL2``: This is an optional build option which specifies the path to BL2 55 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 56 built. 57 58- ``BL2U``: This is an optional build option which specifies the path to 59 BL2U image. In this case, the BL2U in TF-A will not be built. 60 61- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 62 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 63 entrypoint) or 1 (CPU reset to BL2 entrypoint). 64 The default value is 0. 65 66- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 67 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 68 true in a 4-world system where RESET_TO_BL2 is 0. 69 70- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 71 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 72 73- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 74 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 75 the RW sections in RAM, while leaving the RO sections in place. This option 76 enable this use-case. For now, this option is only supported 77 when RESET_TO_BL2 is set to '1'. 78 79- ``BL31``: This is an optional build option which specifies the path to 80 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 81 be built. 82 83- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 84 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 85 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 86 87- ``BL32``: This is an optional build option which specifies the path to 88 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 89 be built. 90 91- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 92 Trusted OS Extra1 image for the ``fip`` target. 93 94- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 95 Trusted OS Extra2 image for the ``fip`` target. 96 97- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 98 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 99 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 100 101- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 102 ``fip`` target in case TF-A BL2 is used. 103 104- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 105 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 106 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 107 108- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 109 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 110 If enabled, it is needed to use a compiler that supports the option 111 ``-mbranch-protection``. Selects the branch protection features to use: 112- 0: Default value turns off all types of branch protection 113- 1: Enables all types of branch protection features 114- 2: Return address signing to its standard level 115- 3: Extend the signing to include leaf functions 116- 4: Turn on branch target identification mechanism 117 118 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 119 and resulting PAuth/BTI features. 120 121 +-------+--------------+-------+-----+ 122 | Value | GCC option | PAuth | BTI | 123 +=======+==============+=======+=====+ 124 | 0 | none | N | N | 125 +-------+--------------+-------+-----+ 126 | 1 | standard | Y | Y | 127 +-------+--------------+-------+-----+ 128 | 2 | pac-ret | Y | N | 129 +-------+--------------+-------+-----+ 130 | 3 | pac-ret+leaf | Y | N | 131 +-------+--------------+-------+-----+ 132 | 4 | bti | N | Y | 133 +-------+--------------+-------+-----+ 134 135 This option defaults to 0. 136 Note that Pointer Authentication is enabled for Non-secure world 137 irrespective of the value of this option if the CPU supports it. 138 139- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 140 compilation of each build. It must be set to a C string (including quotes 141 where applicable). Defaults to a string that contains the time and date of 142 the compilation. 143 144- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 145 build to be uniquely identified. Defaults to the current git commit id. 146 147- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 148 149- ``CFLAGS``: Extra user options appended on the compiler's command line in 150 addition to the options set by the build system. 151 152- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 153 release several CPUs out of reset. It can take either 0 (several CPUs may be 154 brought up) or 1 (only one CPU will ever be brought up during cold reset). 155 Default is 0. If the platform always brings up a single CPU, there is no 156 need to distinguish between primary and secondary CPUs and the boot path can 157 be optimised. The ``plat_is_my_cpu_primary()`` and 158 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 159 to be implemented in this case. 160 161- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 162 Defaults to ``tbbr``. 163 164- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 165 register state when an unexpected exception occurs during execution of 166 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 167 this is only enabled for a debug build of the firmware. 168 169- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 170 certificate generation tool to create new keys in case no valid keys are 171 present or specified. Allowed options are '0' or '1'. Default is '1'. 172 173- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 174 the AArch32 system registers to be included when saving and restoring the 175 CPU context. The option must be set to 0 for AArch64-only platforms (that 176 is on hardware that does not implement AArch32, or at least not at EL1 and 177 higher ELs). Default value is 1. 178 179- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 180 registers to be included when saving and restoring the CPU context. Default 181 is 0. 182 183- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 184 Memory System Resource Partitioning and Monitoring (MPAM) 185 registers to be included when saving and restoring the CPU context. 186 Default is '0'. 187 188- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 189 registers to be saved/restored when entering/exiting an EL2 execution 190 context. This flag can take values 0 to 2, to align with the 191 ``ENABLE_FEAT`` mechanism. Default value is 0. 192 193- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 194 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 195 to be included when saving and restoring the CPU context as part of world 196 switch. This flag can take values 0 to 2, to align with ``ENABLE_FEAT`` 197 mechanism. Default value is 0. 198 199 Note that Pointer Authentication is enabled for Non-secure world irrespective 200 of the value of this flag if the CPU supports it. 201 202- ``DEBUG``: Chooses between a debug and release build. It can take either 0 203 (release) or 1 (debug) as values. 0 is the default. 204 205- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 206 authenticated decryption algorithm to be used to decrypt firmware/s during 207 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 208 this flag is ``none`` to disable firmware decryption which is an optional 209 feature as per TBBR. 210 211- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 212 of the binary image. If set to 1, then only the ELF image is built. 213 0 is the default. 214 215- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 216 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 217 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 218 mechanism. Default is ``0``. 219 220- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 221 Board Boot authentication at runtime. This option is meant to be enabled only 222 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 223 flag has to be enabled. 0 is the default. 224 225- ``E``: Boolean option to make warnings into errors. Default is 1. 226 227 When specifying higher warnings levels (``W=1`` and higher), this option 228 defaults to 0. This is done to encourage contributors to use them, as they 229 are expected to produce warnings that would otherwise fail the build. New 230 contributions are still expected to build with ``W=0`` and ``E=1`` (the 231 default). 232 233- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 234 the normal boot flow. It must specify the entry point address of the EL3 235 payload. Please refer to the "Booting an EL3 payload" section for more 236 details. 237 238- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 239 (also known as group 1 counters). These are implementation-defined counters, 240 and as such require additional platform configuration. Default is 0. 241 242- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 243 allows platforms with auxiliary counters to describe them via the 244 ``HW_CONFIG`` device tree blob. Default is 0. 245 246- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 247 are compiled out. For debug builds, this option defaults to 1, and calls to 248 ``assert()`` are left in place. For release builds, this option defaults to 0 249 and calls to ``assert()`` function are compiled out. This option can be set 250 independently of ``DEBUG``. It can also be used to hide any auxiliary code 251 that is only required for the assertion and does not fit in the assertion 252 itself. 253 254- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 255 dumps or not. It is supported in both AArch64 and AArch32. However, in 256 AArch32 the format of the frame records are not defined in the AAPCS and they 257 are defined by the implementation. This implementation of backtrace only 258 supports the format used by GCC when T32 interworking is disabled. For this 259 reason enabling this option in AArch32 will force the compiler to only 260 generate A32 code. This option is enabled by default only in AArch64 debug 261 builds, but this behaviour can be overridden in each platform's Makefile or 262 in the build command line. 263 264- ``ENABLE_FEAT`` 265 The Arm architecture defines several architecture extension features, 266 named FEAT_xxx in the architecure manual. Some of those features require 267 setup code in higher exception levels, other features might be used by TF-A 268 code itself. 269 Most of the feature flags defined in the TF-A build system permit to take 270 the values 0, 1 or 2, with the following meaning: 271 272 :: 273 274 ENABLE_FEAT_* = 0: Feature is disabled statically at compile time. 275 ENABLE_FEAT_* = 1: Feature is enabled unconditionally at compile time. 276 ENABLE_FEAT_* = 2: Feature is enabled, but checked at runtime. 277 278 When setting the flag to 0, the feature is disabled during compilation, 279 and the compiler's optimisation stage and the linker will try to remove 280 as much of this code as possible. 281 If it is defined to 1, the code will use the feature unconditionally, so the 282 CPU is expected to support that feature. The FEATURE_DETECTION debug 283 feature, if enabled, will verify this. 284 If the feature flag is set to 2, support for the feature will be compiled 285 in, but its existence will be checked at runtime, so it works on CPUs with 286 or without the feature. This is mostly useful for platforms which either 287 support multiple different CPUs, or where the CPU is configured at runtime, 288 like in emulators. 289 290- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 291 extensions. This flag can take the values 0 to 2, to align with the 292 ``ENABLE_FEAT`` mechanism. This is an optional architectural feature 293 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 294 and this option can be used to enable this feature on those systems as well. 295 This flag can take the values 0 to 2, the default is 0. 296 297- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 298 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 299 onwards. This flag can take the values 0 to 2, to align with the 300 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 301 302- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 303 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 304 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 305 optional feature available on Arm v8.0 onwards. This flag can take values 306 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 307 Default value is ``0``. 308 309- ``ENABLE_FEAT_CSV2_3``: Numeric value to enable support for ``FEAT_CSV2_3`` 310 extension. This feature is supported in AArch64 state only and is an optional 311 feature available in Arm v8.0 implementations. 312 ``FEAT_CSV2_3`` implies the implementation of ``FEAT_CSV2_2``. 313 The flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 314 mechanism. Default value is ``0``. 315 316- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 317 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 318 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 319 and upwards. This flag can take the values 0 to 2, to align with the 320 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 321 322- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 323 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 324 Physical Offset register) during EL2 to EL3 context save/restore operations. 325 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 326 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 327 mechanism. Default value is ``0``. 328 329- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 330 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 331 Read Trap Register) during EL2 to EL3 context save/restore operations. 332 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 333 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 334 mechanism. Default value is ``0``. 335 336- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 337 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 338 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 339 mandatory architectural feature and is enabled from v8.7 and upwards. This 340 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 341 mechanism. Default value is ``0``. 342 343- ``ENABLE_FEAT_MTE``: Numeric value to enable Memory Tagging Extension 344 if the platform wants to use this feature in the Secure world and MTE is 345 enabled at ELX. This flag can take values 0 to 2, to align with the 346 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 347 348- ``ENABLE_FEAT_MTE_PERM``: Numeric value to enable support for 349 ``FEAT_MTE_PERM``, which introduces Allocation tag access permission to 350 memory region attributes. ``FEAT_MTE_PERM`` is a optional architectural 351 feature available from v8.9 and upwards. This flag can take the values 0 to 352 2, to align with the ``ENABLE_FEAT`` mechanism. Default value is 353 ``0``. 354 355- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 356 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 357 permission fault for any privileged data access from EL1/EL2 to virtual 358 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 359 mandatory architectural feature and is enabled from v8.1 and upwards. This 360 flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 361 mechanism. Default value is ``0``. 362 363- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 364 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 365 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 366 mechanism. Default value is ``0``. 367 368- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 369 extension. This feature is only supported in AArch64 state. This flag can 370 take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 371 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 372 Armv8.5 onwards. 373 374- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 375 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 376 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 377 later CPUs. It is enabled from v8.5 and upwards and if needed can be 378 overidden from platforms explicitly. 379 380- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 381 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 382 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 383 mechanism. Default is ``0``. 384 385- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 386 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 387 available on Arm v8.6. This flag can take values 0 to 2, to align with the 388 ``ENABLE_FEAT`` mechanism. Default is ``0``. 389 390 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 391 delayed by the amount of value in ``TWED_DELAY``. 392 393- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 394 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 395 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 396 architectural feature and is enabled from v8.1 and upwards. It can take 397 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 398 Default value is ``0``. 399 400- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 401 allow access to TCR2_EL2 (extended translation control) from EL2 as 402 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 403 mandatory architectural feature and is enabled from v8.9 and upwards. This 404 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 405 mechanism. Default value is ``0``. 406 407- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 408 at EL2 and below, and context switch relevant registers. This flag 409 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 410 mechanism. Default value is ``0``. 411 412- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 413 at EL2 and below, and context switch relevant registers. This flag 414 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 415 mechanism. Default value is ``0``. 416 417- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 418 at EL2 and below, and context switch relevant registers. This flag 419 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 420 mechanism. Default value is ``0``. 421 422- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 423 at EL2 and below, and context switch relevant registers. This flag 424 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 425 mechanism. Default value is ``0``. 426 427- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 428 allow use of Guarded Control Stack from EL2 as well as adding the GCS 429 registers to the EL2 context save/restore operations. This flag can take 430 the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 431 Default value is ``0``. 432 433- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 434 support in GCC for TF-A. This option is currently only supported for 435 AArch64. Default is 0. 436 437- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 438 feature. MPAM is an optional Armv8.4 extension that enables various memory 439 system components and resources to define partitions; software running at 440 various ELs can assign themselves to desired partition to control their 441 performance aspects. 442 443 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 444 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 445 access their own MPAM registers without trapping into EL3. This option 446 doesn't make use of partitioning in EL3, however. Platform initialisation 447 code should configure and use partitions in EL3 as required. This option 448 defaults to ``2`` since MPAM is enabled by default for NS world only. 449 The flag is automatically disabled when the target 450 architecture is AArch32. 451 452- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 453 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 454 firmware to detect and limit high activity events to assist in SoC processor 455 power domain dynamic power budgeting and limit the triggering of whole-rail 456 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 457 458- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 459 allows platforms with cores supporting MPMM to describe them via the 460 ``HW_CONFIG`` device tree blob. Default is 0. 461 462- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 463 support within generic code in TF-A. This option is currently only supported 464 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 465 in BL32 (SP_min) for AARCH32. Default is 0. 466 467- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 468 Measurement Framework(PMF). Default is 0. 469 470- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 471 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 472 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 473 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 474 software. 475 476- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 477 instrumentation which injects timestamp collection points into TF-A to 478 allow runtime performance to be measured. Currently, only PSCI is 479 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 480 as well. Default is 0. 481 482- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 483 extensions. This is an optional architectural feature for AArch64. 484 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 485 mechanism. The default is 2 but is automatically disabled when the target 486 architecture is AArch32. 487 488- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 489 (SVE) for the Non-secure world only. SVE is an optional architectural feature 490 for AArch64. Note that when SVE is enabled for the Non-secure world, access 491 to SIMD and floating-point functionality from the Secure world is disabled by 492 default and controlled with ENABLE_SVE_FOR_SWD. 493 This is to avoid corruption of the Non-secure world data in the Z-registers 494 which are aliased by the SIMD and FP registers. The build option is not 495 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 496 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` 497 enabled. This flag can take the values 0 to 2, to align with the 498 ``ENABLE_FEAT`` mechanism. At this time, this build option cannot be 499 used on systems that have SPM_MM enabled. The default is 1. 500 501- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 502 SVE is an optional architectural feature for AArch64. Note that this option 503 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is 504 automatically disabled when the target architecture is AArch32. 505 506- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 507 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 508 default value is set to "none". "strong" is the recommended stack protection 509 level if this feature is desired. "none" disables the stack protection. For 510 all values other than "none", the ``plat_get_stack_protector_canary()`` 511 platform hook needs to be implemented. The value is passed as the last 512 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 513 514- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 515 flag depends on ``DECRYPTION_SUPPORT`` build flag. 516 517- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 518 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 519 520- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 521 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 522 on ``DECRYPTION_SUPPORT`` build flag. 523 524- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 525 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 526 build flag. 527 528- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 529 deprecated platform APIs, helper functions or drivers within Trusted 530 Firmware as error. It can take the value 1 (flag the use of deprecated 531 APIs as error) or 0. The default is 0. 532 533- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 534 configure an Arm® Ethos™-N NPU. To use this service the target platform's 535 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 536 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 537 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 538 539- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 540 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 541 ``TRUSTED_BOARD_BOOT`` to be enabled. 542 543- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 544 (```ethosn.bin```). This firmware image will be included in the FIP and 545 loaded at runtime. 546 547- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 548 targeted at EL3. When set ``0`` (default), no exceptions are expected or 549 handled at EL3, and a panic will result. The exception to this rule is when 550 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 551 occuring during normal world execution, are trapped to EL3. Any exception 552 trapped during secure world execution are trapped to the SPMC. This is 553 supported only for AArch64 builds. 554 555- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 556 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 557 Default value is 40 (LOG_LEVEL_INFO). 558 559- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 560 injection from lower ELs, and this build option enables lower ELs to use 561 Error Records accessed via System Registers to inject faults. This is 562 applicable only to AArch64 builds. 563 564 This feature is intended for testing purposes only, and is advisable to keep 565 disabled for production images. 566 567- ``FIP_NAME``: This is an optional build option which specifies the FIP 568 filename for the ``fip`` target. Default is ``fip.bin``. 569 570- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 571 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 572 573- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 574 575 :: 576 577 0: Encryption is done with Secret Symmetric Key (SSK) which is common 578 for a class of devices. 579 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 580 unique per device. 581 582 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 583 584- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 585 tool to create certificates as per the Chain of Trust described in 586 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 587 include the certificates in the FIP and FWU_FIP. Default value is '0'. 588 589 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 590 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 591 the corresponding certificates, and to include those certificates in the 592 FIP and FWU_FIP. 593 594 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 595 images will not include support for Trusted Board Boot. The FIP will still 596 include the corresponding certificates. This FIP can be used to verify the 597 Chain of Trust on the host machine through other mechanisms. 598 599 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 600 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 601 will not include the corresponding certificates, causing a boot failure. 602 603- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 604 inherent support for specific EL3 type interrupts. Setting this build option 605 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 606 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 607 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 608 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 609 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 610 the Secure Payload interrupts needs to be synchronously handed over to Secure 611 EL1 for handling. The default value of this option is ``0``, which means the 612 Group 0 interrupts are assumed to be handled by Secure EL1. 613 614- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 615 Interrupts, resulting from errors in NS world, will be always trapped in 616 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 617 will be trapped in the current exception level (or in EL1 if the current 618 exception level is EL0). 619 620- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 621 software operations are required for CPUs to enter and exit coherency. 622 However, newer systems exist where CPUs' entry to and exit from coherency 623 is managed in hardware. Such systems require software to only initiate these 624 operations, and the rest is managed in hardware, minimizing active software 625 management. In such systems, this boolean option enables TF-A to carry out 626 build and run-time optimizations during boot and power management operations. 627 This option defaults to 0 and if it is enabled, then it implies 628 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 629 630 If this flag is disabled while the platform which TF-A is compiled for 631 includes cores that manage coherency in hardware, then a compilation error is 632 generated. This is based on the fact that a system cannot have, at the same 633 time, cores that manage coherency in hardware and cores that don't. In other 634 words, a platform cannot have, at the same time, cores that require 635 ``HW_ASSISTED_COHERENCY=1`` and cores that require 636 ``HW_ASSISTED_COHERENCY=0``. 637 638 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 639 translation library (xlat tables v2) must be used; version 1 of translation 640 library is not supported. 641 642- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 643 implementation defined system register accesses from lower ELs. Default 644 value is ``0``. 645 646- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 647 bottom, higher addresses at the top. This build flag can be set to '1' to 648 invert this behavior. Lower addresses will be printed at the top and higher 649 addresses at the bottom. 650 651- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 652 used for generating the PKCS keys and subsequent signing of the certificate. 653 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 654 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 655 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 656 compatibility. The default value of this flag is ``rsa`` which is the TBBR 657 compliant PKCS#1 RSA 2.1 scheme. 658 659- ``KEY_SIZE``: This build flag enables the user to select the key size for 660 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 661 depend on the chosen algorithm and the cryptographic module. 662 663 +---------------------------+------------------------------------+ 664 | KEY_ALG | Possible key sizes | 665 +===========================+====================================+ 666 | rsa | 1024 , 2048 (default), 3072, 4096 | 667 +---------------------------+------------------------------------+ 668 | ecdsa | 256 (default), 384 | 669 +---------------------------+------------------------------------+ 670 | ecdsa-brainpool-regular | unavailable | 671 +---------------------------+------------------------------------+ 672 | ecdsa-brainpool-twisted | unavailable | 673 +---------------------------+------------------------------------+ 674 675- ``HASH_ALG``: This build flag enables the user to select the secure hash 676 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 677 The default value of this flag is ``sha256``. 678 679- ``LDFLAGS``: Extra user options appended to the linkers' command line in 680 addition to the one set by the build system. 681 682- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 683 output compiled into the build. This should be one of the following: 684 685 :: 686 687 0 (LOG_LEVEL_NONE) 688 10 (LOG_LEVEL_ERROR) 689 20 (LOG_LEVEL_NOTICE) 690 30 (LOG_LEVEL_WARNING) 691 40 (LOG_LEVEL_INFO) 692 50 (LOG_LEVEL_VERBOSE) 693 694 All log output up to and including the selected log level is compiled into 695 the build. The default value is 40 in debug builds and 20 in release builds. 696 697- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 698 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 699 provide trust that the code taking the measurements and recording them has 700 not been tampered with. 701 702 This option defaults to 0. 703 704- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 705 options to the compiler. An example usage: 706 707 .. code:: make 708 709 MARCH_DIRECTIVE := -march=armv8.5-a 710 711- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 712 options to the compiler currently supporting only of the options. 713 GCC documentation: 714 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 715 716 An example usage: 717 718 .. code:: make 719 720 HARDEN_SLS := 1 721 722 This option defaults to 0. 723 724- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 725 specifies a file that contains the Non-Trusted World private key in PEM 726 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 727 will be used to save the key. 728 729- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 730 optional. It is only needed if the platform makefile specifies that it 731 is required in order to build the ``fwu_fip`` target. 732 733- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 734 contents upon world switch. It can take either 0 (don't save and restore) or 735 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 736 wants the timer registers to be saved and restored. 737 738- ``OPTEE_SP_FW_CONFIG``: DTC build flag to include OP-TEE as SP in 739 tb_fw_config device tree. This flag is defined only when 740 ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern optee_sp. 741 742- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 743 for the BL image. It can be either 0 (include) or 1 (remove). The default 744 value is 0. 745 746- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 747 the underlying hardware is not a full PL011 UART but a minimally compliant 748 generic UART, which is a subset of the PL011. The driver will not access 749 any register that is not part of the SBSA generic UART specification. 750 Default value is 0 (a full PL011 compliant UART is present). 751 752- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 753 must be subdirectory of any depth under ``plat/``, and must contain a 754 platform makefile named ``platform.mk``. For example, to build TF-A for the 755 Arm Juno board, select PLAT=juno. 756 757- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 758 each core as well as the global context. The data includes the memory used 759 by each world and each privileged exception level. This build option is 760 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 761 762- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 763 instead of the normal boot flow. When defined, it must specify the entry 764 point address for the preloaded BL33 image. This option is incompatible with 765 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 766 over ``PRELOADED_BL33_BASE``. 767 768- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 769 vector address can be programmed or is fixed on the platform. It can take 770 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 771 programmable reset address, it is expected that a CPU will start executing 772 code directly at the right address, both on a cold and warm reset. In this 773 case, there is no need to identify the entrypoint on boot and the boot path 774 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 775 does not need to be implemented in this case. 776 777- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 778 possible for the PSCI power-state parameter: original and extended State-ID 779 formats. This flag if set to 1, configures the generic PSCI layer to use the 780 extended format. The default value of this flag is 0, which means by default 781 the original power-state format is used by the PSCI implementation. This flag 782 should be specified by the platform makefile and it governs the return value 783 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 784 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 785 set to 1 as well. 786 787- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 788 OS-initiated mode. This option defaults to 0. 789 790- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features 791 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 792 or later CPUs. This flag can take the values 0 or 1. The default value is 0. 793 NOTE: This flag enables use of IESB capability to reduce entry latency into 794 EL3 even when RAS error handling is not performed on the platform. Hence this 795 flag is recommended to be turned on Armv8.2 and later CPUs. 796 797- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 798 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 799 entrypoint) or 1 (CPU reset to BL31 entrypoint). 800 The default value is 0. 801 802- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 803 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 804 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 805 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 806 807- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 808 file that contains the ROT private key in PEM format or a PKCS11 URI and 809 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 810 accepted and it will be used to save the key. 811 812- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 813 certificate generation tool to save the keys used to establish the Chain of 814 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 815 816- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 817 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 818 target. 819 820- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 821 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 822 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 823 824- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 825 optional. It is only needed if the platform makefile specifies that it 826 is required in order to build the ``fwu_fip`` target. 827 828- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 829 Delegated Exception Interface to BL31 image. This defaults to ``0``. 830 831 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 832 set to ``1``. 833 834- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 835 isolated on separate memory pages. This is a trade-off between security and 836 memory usage. See "Isolating code and read-only data on separate memory 837 pages" section in :ref:`Firmware Design`. This flag is disabled by default 838 and affects all BL images. 839 840- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 841 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 842 allocated in RAM discontiguous from the loaded firmware image. When set, the 843 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 844 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 845 sections are placed in RAM immediately following the loaded firmware image. 846 847- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 848 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 849 discontiguous from loaded firmware images. When set, the platform need to 850 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 851 flag is disabled by default and NOLOAD sections are placed in RAM immediately 852 following the loaded firmware image. 853 854- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 855 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 856 UEFI+ACPI this can provide a certain amount of OS forward compatibility 857 with newer platforms that aren't ECAM compliant. 858 859- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 860 This build option is only valid if ``ARCH=aarch64``. The value should be 861 the path to the directory containing the SPD source, relative to 862 ``services/spd/``; the directory is expected to contain a makefile called 863 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 864 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 865 cannot be enabled when the ``SPM_MM`` option is enabled. 866 867- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 868 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 869 execution in BL1 just before handing over to BL31. At this point, all 870 firmware images have been loaded in memory, and the MMU and caches are 871 turned off. Refer to the "Debugging options" section for more details. 872 873- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 874 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 875 component runs at the EL3 exception level. The default value is ``0`` ( 876 disabled). This configuration supports pre-Armv8.4 platforms (aka not 877 implementing the ``FEAT_SEL2`` extension). 878 879- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 880 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 881 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 882 883- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 884 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 885 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 886 mechanism should be used. 887 888- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 889 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 890 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 891 extension. This is the default when enabling the SPM Dispatcher. When 892 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 893 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 894 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 895 extension). 896 897- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 898 Partition Manager (SPM) implementation. The default value is ``0`` 899 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 900 enabled (``SPD=spmd``). 901 902- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 903 description of secure partitions. The build system will parse this file and 904 package all secure partition blobs into the FIP. This file is not 905 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 906 907- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 908 secure interrupts (caught through the FIQ line). Platforms can enable 909 this directive if they need to handle such interruption. When enabled, 910 the FIQ are handled in monitor mode and non secure world is not allowed 911 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 912 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 913 914- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 915 Platforms can configure this if they need to lower the hardware 916 limit, for example due to asymmetric configuration or limitations of 917 software run at lower ELs. The default is the architectural maximum 918 of 2048 which should be suitable for most configurations, the 919 hardware will limit the effective VL to the maximum physically supported 920 VL. 921 922- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 923 Random Number Generator Interface to BL31 image. This defaults to ``0``. 924 925- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 926 Boot feature. When set to '1', BL1 and BL2 images include support to load 927 and verify the certificates and images in a FIP, and BL1 includes support 928 for the Firmware Update. The default value is '0'. Generation and inclusion 929 of certificates in the FIP and FWU_FIP depends upon the value of the 930 ``GENERATE_COT`` option. 931 932 .. warning:: 933 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 934 already exist in disk, they will be overwritten without further notice. 935 936- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 937 specifies a file that contains the Trusted World private key in PEM 938 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 939 it will be used to save the key. 940 941- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 942 synchronous, (see "Initializing a BL32 Image" section in 943 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 944 synchronous method) or 1 (BL32 is initialized using asynchronous method). 945 Default is 0. 946 947- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 948 routing model which routes non-secure interrupts asynchronously from TSP 949 to EL3 causing immediate preemption of TSP. The EL3 is responsible 950 for saving and restoring the TSP context in this routing model. The 951 default routing model (when the value is 0) is to route non-secure 952 interrupts to TSP allowing it to save its context and hand over 953 synchronously to EL3 via an SMC. 954 955 .. note:: 956 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 957 must also be set to ``1``. 958 959- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 960 internal-trusted-storage) as SP in tb_fw_config device tree. 961 962- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 963 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 964 this delay. It can take values in the range (0-15). Default value is ``0`` 965 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 966 Platforms need to explicitly update this value based on their requirements. 967 968- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 969 linker. When the ``LINKER`` build variable points to the armlink linker, 970 this flag is enabled automatically. To enable support for armlink, platforms 971 will have to provide a scatter file for the BL image. Currently, Tegra 972 platforms use the armlink support to compile BL3-1 images. 973 974- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 975 memory region in the BL memory map or not (see "Use of Coherent memory in 976 TF-A" section in :ref:`Firmware Design`). It can take the value 1 977 (Coherent memory region is included) or 0 (Coherent memory region is 978 excluded). Default is 1. 979 980- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 981 firmware configuration framework. This will move the io_policies into a 982 configuration device tree, instead of static structure in the code base. 983 984- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 985 at runtime using fconf. If this flag is enabled, COT descriptors are 986 statically captured in tb_fw_config file in the form of device tree nodes 987 and properties. Currently, COT descriptors used by BL2 are moved to the 988 device tree and COT descriptors used by BL1 are retained in the code 989 base statically. 990 991- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 992 runtime using firmware configuration framework. The platform specific SDEI 993 shared and private events configuration is retrieved from device tree rather 994 than static C structures at compile time. This is only supported if 995 SDEI_SUPPORT build flag is enabled. 996 997- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 998 and Group1 secure interrupts using the firmware configuration framework. The 999 platform specific secure interrupt property descriptor is retrieved from 1000 device tree in runtime rather than depending on static C structure at compile 1001 time. 1002 1003- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1004 This feature creates a library of functions to be placed in ROM and thus 1005 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1006 is 0. 1007 1008- ``V``: Verbose build. If assigned anything other than 0, the build commands 1009 are printed. Default is 0. 1010 1011- ``VERSION_STRING``: String used in the log output for each TF-A image. 1012 Defaults to a string formed by concatenating the version number, build type 1013 and build string. 1014 1015- ``W``: Warning level. Some compiler warning options of interest have been 1016 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1017 each level enabling more warning options. Default is 0. 1018 1019 This option is closely related to the ``E`` option, which enables 1020 ``-Werror``. 1021 1022 - ``W=0`` (default) 1023 1024 Enables a wide assortment of warnings, most notably ``-Wall`` and 1025 ``-Wextra``, as well as various bad practices and things that are likely to 1026 result in errors. Includes some compiler specific flags. No warnings are 1027 expected at this level for any build. 1028 1029 - ``W=1`` 1030 1031 Enables warnings we want the generic build to include but are too time 1032 consuming to fix at the moment. It re-enables warnings taken out for 1033 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1034 to eventually be merged into ``W=0``. Some warnings are expected on some 1035 builds, but new contributions should not introduce new ones. 1036 1037 - ``W=2`` (recommended) 1038 1039 Enables warnings we want the generic build to include but cannot be enabled 1040 due to external libraries. This level is expected to eventually be merged 1041 into ``W=0``. Lots of warnings are expected, primarily from external 1042 libraries like zlib and compiler-rt, but new controbutions should not 1043 introduce new ones. 1044 1045 - ``W=3`` 1046 1047 Enables warnings that are informative but not necessary and generally too 1048 verbose and frequently ignored. A very large number of warnings are 1049 expected. 1050 1051 The exact set of warning flags depends on the compiler and TF-A warning 1052 level, however they are all succinctly set in the top-level Makefile. Please 1053 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1054 individual flags. 1055 1056- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1057 the CPU after warm boot. This is applicable for platforms which do not 1058 require interconnect programming to enable cache coherency (eg: single 1059 cluster platforms). If this option is enabled, then warm boot path 1060 enables D-caches immediately after enabling MMU. This option defaults to 0. 1061 1062- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1063 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1064 default value of this flag is ``no``. Note this option must be enabled only 1065 for ARM architecture greater than Armv8.5-A. 1066 1067- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1068 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1069 The default value of this flag is ``0``. 1070 1071 ``AT`` speculative errata workaround disables stage1 page table walk for 1072 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1073 produces either the correct result or failure without TLB allocation. 1074 1075 This boolean option enables errata for all below CPUs. 1076 1077 +---------+--------------+-------------------------+ 1078 | Errata | CPU | Workaround Define | 1079 +=========+==============+=========================+ 1080 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1081 +---------+--------------+-------------------------+ 1082 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1083 +---------+--------------+-------------------------+ 1084 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1085 +---------+--------------+-------------------------+ 1086 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1087 +---------+--------------+-------------------------+ 1088 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1089 +---------+--------------+-------------------------+ 1090 1091 .. note:: 1092 This option is enabled by build only if platform sets any of above defines 1093 mentioned in ’Workaround Define' column in the table. 1094 If this option is enabled for the EL3 software then EL2 software also must 1095 implement this workaround due to the behaviour of the errata mentioned 1096 in new SDEN document which will get published soon. 1097 1098- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1099 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1100 This flag is disabled by default. 1101 1102- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1103 host machine where a custom installation of OpenSSL is located, which is used 1104 to build the certificate generation, firmware encryption and FIP tools. If 1105 this option is not set, the default OS installation will be used. 1106 1107- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1108 functions that wait for an arbitrary time length (udelay and mdelay). The 1109 default value is 0. 1110 1111- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1112 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1113 optional architectural feature for AArch64. This flag can take the values 1114 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0 1115 and it is automatically disabled when the target architecture is AArch32. 1116 1117- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1118 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1119 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1120 feature for AArch64. This flag can take the values 0 to 2, to align with the 1121 ``ENABLE_FEAT`` mechanism. The default is 0 and it is automatically 1122 disabled when the target architecture is AArch32. 1123 1124- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1125 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1126 but unused). This feature is available if trace unit such as ETMv4.x, and 1127 ETE(extending ETM feature) is implemented. This flag can take the values 1128 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0. 1129 1130- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1131 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1132 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1133 with the ``ENABLE_FEAT`` mechanism. This flag is disabled by default. 1134 1135- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1136 ``plat_can_cmo`` which will return zero if cache management operations should 1137 be skipped and non-zero otherwise. By default, this option is disabled which 1138 means platform hook won't be checked and CMOs will always be performed when 1139 related functions are called. 1140 1141- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1142 firmware interface for the BL31 image. By default its disabled (``0``). 1143 1144- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1145 errata mitigation for platforms with a non-arm interconnect using the errata 1146 ABI. By default its disabled (``0``). 1147 1148- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1149 driver(s). By default it is disabled (``0``) because it constitutes an attack 1150 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1151 This option should only be enabled on a need basis if there is a use case for 1152 reading characters from the console. 1153 1154GICv3 driver options 1155-------------------- 1156 1157GICv3 driver files are included using directive: 1158 1159``include drivers/arm/gic/v3/gicv3.mk`` 1160 1161The driver can be configured with the following options set in the platform 1162makefile: 1163 1164- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1165 Enabling this option will add runtime detection support for the 1166 GIC-600, so is safe to select even for a GIC500 implementation. 1167 This option defaults to 0. 1168 1169- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1170 for GIC-600 AE. Enabling this option will introduce support to initialize 1171 the FMU. Platforms should call the init function during boot to enable the 1172 FMU and its safety mechanisms. This option defaults to 0. 1173 1174- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1175 functionality. This option defaults to 0 1176 1177- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1178 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1179 functions. This is required for FVP platform which need to simulate GIC save 1180 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1181 1182- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1183 This option defaults to 0. 1184 1185- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1186 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1187 1188Debugging options 1189----------------- 1190 1191To compile a debug version and make the build more verbose use 1192 1193.. code:: shell 1194 1195 make PLAT=<platform> DEBUG=1 V=1 all 1196 1197AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1198(for example Arm-DS) might not support this and may need an older version of 1199DWARF symbols to be emitted by GCC. This can be achieved by using the 1200``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1201the version to 4 is recommended for Arm-DS. 1202 1203When debugging logic problems it might also be useful to disable all compiler 1204optimizations by using ``-O0``. 1205 1206.. warning:: 1207 Using ``-O0`` could cause output images to be larger and base addresses 1208 might need to be recalculated (see the **Memory layout on Arm development 1209 platforms** section in the :ref:`Firmware Design`). 1210 1211Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1212``LDFLAGS``: 1213 1214.. code:: shell 1215 1216 CFLAGS='-O0 -gdwarf-2' \ 1217 make PLAT=<platform> DEBUG=1 V=1 all 1218 1219Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1220ignored as the linker is called directly. 1221 1222It is also possible to introduce an infinite loop to help in debugging the 1223post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1224``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1225section. In this case, the developer may take control of the target using a 1226debugger when indicated by the console output. When using Arm-DS, the following 1227commands can be used: 1228 1229:: 1230 1231 # Stop target execution 1232 interrupt 1233 1234 # 1235 # Prepare your debugging environment, e.g. set breakpoints 1236 # 1237 1238 # Jump over the debug loop 1239 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1240 1241 # Resume execution 1242 continue 1243 1244.. _build_options_experimental: 1245 1246Experimental build options 1247--------------------------- 1248 1249Common build options 1250~~~~~~~~~~~~~~~~~~~~ 1251 1252- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1253 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1254 the measurements and recording them as per `PSA DRTM specification`_. For 1255 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1256 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1257 should have mechanism to authenticate BL31. This option defaults to 0. 1258 1259- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 1260 Management Extension. This flag can take the values 0 to 2, to align with 1261 the ``ENABLE_FEAT`` mechanism. Default value is 0. 1262 1263- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1264 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1265 registers so are enabled together. Using this option without 1266 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1267 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1268 superset of SVE. SME is an optional architectural feature for AArch64. 1269 At this time, this build option cannot be used on systems that have 1270 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1271 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 1272 mechanism. Default is 0. 1273 1274- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1275 version 2 (SME2) for the non-secure world only. SME2 is an optional 1276 architectural feature for AArch64. 1277 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1278 accesses will still be trapped. This flag can take the values 0 to 2, to 1279 align with the ``ENABLE_FEAT`` mechanism. Default is 0. 1280 1281- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1282 Extension for secure world. Used along with SVE and FPU/SIMD. 1283 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1284 Default is 0. 1285 1286- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1287 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1288 for logical partitions in EL3, managed by the SPMD as defined in the 1289 FF-A v1.2 specification. This flag is disabled by default. This flag 1290 must not be used if ``SPMC_AT_EL3`` is enabled. 1291 1292- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1293 verification mechanism. This is a debug feature that compares the 1294 architectural features enabled through the feature specific build flags 1295 (ENABLE_FEAT_xxx) with the features actually available on the CPU running, 1296 and reports any discrepancies. 1297 This flag will also enable errata ordering checking for ``DEBUG`` builds. 1298 1299 It is expected that this feature is only used for flexible platforms like 1300 software emulators, or for hardware platforms at bringup time, to verify 1301 that the configured feature set matches the CPU. 1302 The ``FEATURE_DETECTION`` macro is disabled by default. 1303 1304- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1305 The platform will use PSA compliant Crypto APIs during authentication and 1306 image measurement process by enabling this option. It uses APIs defined as 1307 per the `PSA Crypto API specification`_. This feature is only supported if 1308 using MbedTLS 3.x version. It is disabled (``0``) by default. 1309 1310- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1311 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1312 This defaults to ``0``. Current implementation follows the Firmware Handoff 1313 specification v0.9. 1314 1315- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1316 interface through BL31 as a SiP SMC function. 1317 Default is disabled (0). 1318 1319Firmware update options 1320~~~~~~~~~~~~~~~~~~~~~~~ 1321 1322- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1323 `PSA FW update specification`_. The default value is 0. 1324 PSA firmware update implementation has few limitations, such as: 1325 1326 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1327 be updated, then it should be done through another platform-defined 1328 mechanism. 1329 1330 - It assumes the platform's hardware supports CRC32 instructions. 1331 1332- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1333 in defining the firmware update metadata structure. This flag is by default 1334 set to '2'. 1335 1336- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1337 firmware bank. Each firmware bank must have the same number of images as per 1338 the `PSA FW update specification`_. 1339 This flag is used in defining the firmware update metadata structure. This 1340 flag is by default set to '1'. 1341 1342-------------- 1343 1344*Copyright (c) 2019-2024, Arm Limited. All rights reserved.* 1345 1346.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1347.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ 1348.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1349.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1350.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1351.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1352.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1353