1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <drivers/auth/auth_mod.h> 18 #include <drivers/auth/crypto_mod.h> 19 #include <drivers/console.h> 20 #include <lib/bootmarker_capture.h> 21 #include <lib/cpus/errata.h> 22 #include <lib/pmf/pmf.h> 23 #include <lib/utils.h> 24 #include <plat/common/platform.h> 25 #include <smccc_helpers.h> 26 #include <tools_share/uuid.h> 27 28 #include "bl1_private.h" 29 30 static void bl1_load_bl2(void); 31 32 #if ENABLE_PAUTH 33 uint64_t bl1_apiakey[2]; 34 #endif 35 36 #if ENABLE_RUNTIME_INSTRUMENTATION 37 PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID, 38 BL_TOTAL_IDS, PMF_DUMP_ENABLE) 39 #endif 40 41 /******************************************************************************* 42 * Helper utility to calculate the BL2 memory layout taking into consideration 43 * the BL1 RW data assuming that it is at the top of the memory layout. 44 ******************************************************************************/ 45 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 46 meminfo_t *bl2_mem_layout) 47 { 48 assert(bl1_mem_layout != NULL); 49 assert(bl2_mem_layout != NULL); 50 51 /* 52 * Remove BL1 RW data from the scope of memory visible to BL2. 53 * This is assuming BL1 RW data is at the top of bl1_mem_layout. 54 */ 55 assert(BL1_RW_BASE > bl1_mem_layout->total_base); 56 bl2_mem_layout->total_base = bl1_mem_layout->total_base; 57 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; 58 59 flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t)); 60 } 61 62 /******************************************************************************* 63 * Setup function for BL1. 64 ******************************************************************************/ 65 void bl1_setup(void) 66 { 67 /* Perform early platform-specific setup */ 68 bl1_early_platform_setup(); 69 70 /* Perform late platform-specific setup */ 71 bl1_plat_arch_setup(); 72 73 #if CTX_INCLUDE_PAUTH_REGS 74 /* 75 * Assert that the ARMv8.3-PAuth registers are present or an access 76 * fault will be triggered when they are being saved or restored. 77 */ 78 assert(is_armv8_3_pauth_present()); 79 #endif /* CTX_INCLUDE_PAUTH_REGS */ 80 } 81 82 /******************************************************************************* 83 * Function to perform late architectural and platform specific initialization. 84 * It also queries the platform to load and run next BL image. Only called 85 * by the primary cpu after a cold boot. 86 ******************************************************************************/ 87 void bl1_main(void) 88 { 89 unsigned int image_id; 90 91 #if ENABLE_RUNTIME_INSTRUMENTATION 92 PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_ENTRY, PMF_CACHE_MAINT); 93 #endif 94 95 /* Announce our arrival */ 96 NOTICE(FIRMWARE_WELCOME_STR); 97 NOTICE("BL1: %s\n", version_string); 98 NOTICE("BL1: %s\n", build_message); 99 100 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT); 101 102 print_errata_status(); 103 104 #if ENABLE_ASSERTIONS 105 u_register_t val; 106 /* 107 * Ensure that MMU/Caches and coherency are turned on 108 */ 109 #ifdef __aarch64__ 110 val = read_sctlr_el3(); 111 #else 112 val = read_sctlr(); 113 #endif 114 assert((val & SCTLR_M_BIT) != 0); 115 assert((val & SCTLR_C_BIT) != 0); 116 assert((val & SCTLR_I_BIT) != 0); 117 /* 118 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the 119 * provided platform value 120 */ 121 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; 122 /* 123 * If CWG is zero, then no CWG information is available but we can 124 * at least check the platform value is less than the architectural 125 * maximum. 126 */ 127 if (val != 0) 128 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); 129 else 130 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); 131 #endif /* ENABLE_ASSERTIONS */ 132 133 /* Perform remaining generic architectural setup from EL3 */ 134 bl1_arch_setup(); 135 136 crypto_mod_init(); 137 138 /* Initialize authentication module */ 139 auth_mod_init(); 140 141 /* Initialize the measured boot */ 142 bl1_plat_mboot_init(); 143 144 /* Perform platform setup in BL1. */ 145 bl1_platform_setup(); 146 147 #if ENABLE_PAUTH 148 /* Store APIAKey_EL1 key */ 149 bl1_apiakey[0] = read_apiakeylo_el1(); 150 bl1_apiakey[1] = read_apiakeyhi_el1(); 151 #endif /* ENABLE_PAUTH */ 152 153 /* Get the image id of next image to load and run. */ 154 image_id = bl1_plat_get_next_image_id(); 155 156 /* 157 * We currently interpret any image id other than 158 * BL2_IMAGE_ID as the start of firmware update. 159 */ 160 if (image_id == BL2_IMAGE_ID) 161 bl1_load_bl2(); 162 else 163 NOTICE("BL1-FWU: *******FWU Process Started*******\n"); 164 165 /* Teardown the measured boot driver */ 166 bl1_plat_mboot_finish(); 167 168 bl1_prepare_next_image(image_id); 169 170 #if ENABLE_RUNTIME_INSTRUMENTATION 171 PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_EXIT, PMF_CACHE_MAINT); 172 #endif 173 174 console_flush(); 175 } 176 177 /******************************************************************************* 178 * This function locates and loads the BL2 raw binary image in the trusted SRAM. 179 * Called by the primary cpu after a cold boot. 180 * TODO: Add support for alternative image load mechanism e.g using virtio/elf 181 * loader etc. 182 ******************************************************************************/ 183 static void bl1_load_bl2(void) 184 { 185 image_desc_t *desc; 186 image_info_t *info; 187 int err; 188 189 /* Get the image descriptor */ 190 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); 191 assert(desc != NULL); 192 193 /* Get the image info */ 194 info = &desc->image_info; 195 INFO("BL1: Loading BL2\n"); 196 197 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID); 198 if (err != 0) { 199 ERROR("Failure in pre image load handling of BL2 (%d)\n", err); 200 plat_error_handler(err); 201 } 202 203 err = load_auth_image(BL2_IMAGE_ID, info); 204 if (err != 0) { 205 ERROR("Failed to load BL2 firmware.\n"); 206 plat_error_handler(err); 207 } 208 209 /* Allow platform to handle image information. */ 210 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID); 211 if (err != 0) { 212 ERROR("Failure in post image load handling of BL2 (%d)\n", err); 213 plat_error_handler(err); 214 } 215 216 NOTICE("BL1: Booting BL2\n"); 217 } 218 219 /******************************************************************************* 220 * Function called just before handing over to the next BL to inform the user 221 * about the boot progress. In debug mode, also print details about the BL 222 * image's execution context. 223 ******************************************************************************/ 224 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info) 225 { 226 #ifdef __aarch64__ 227 NOTICE("BL1: Booting BL31\n"); 228 #else 229 NOTICE("BL1: Booting BL32\n"); 230 #endif /* __aarch64__ */ 231 print_entry_point_info(bl_ep_info); 232 } 233 234 #if SPIN_ON_BL1_EXIT 235 void print_debug_loop_message(void) 236 { 237 NOTICE("BL1: Debug loop, spinning forever\n"); 238 NOTICE("BL1: Please connect the debugger to continue\n"); 239 } 240 #endif 241 242 /******************************************************************************* 243 * Top level handler for servicing BL1 SMCs. 244 ******************************************************************************/ 245 u_register_t bl1_smc_handler(unsigned int smc_fid, 246 u_register_t x1, 247 u_register_t x2, 248 u_register_t x3, 249 u_register_t x4, 250 void *cookie, 251 void *handle, 252 unsigned int flags) 253 { 254 /* BL1 Service UUID */ 255 DEFINE_SVC_UUID2(bl1_svc_uid, 256 U(0xd46739fd), 0xcb72, 0x9a4d, 0xb5, 0x75, 257 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a); 258 259 260 #if TRUSTED_BOARD_BOOT 261 /* 262 * Dispatch FWU calls to FWU SMC handler and return its return 263 * value 264 */ 265 if (is_fwu_fid(smc_fid)) { 266 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie, 267 handle, flags); 268 } 269 #endif 270 271 switch (smc_fid) { 272 case BL1_SMC_CALL_COUNT: 273 SMC_RET1(handle, BL1_NUM_SMC_CALLS); 274 275 case BL1_SMC_UID: 276 SMC_UUID_RET(handle, bl1_svc_uid); 277 278 case BL1_SMC_VERSION: 279 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER); 280 281 default: 282 WARN("Unimplemented BL1 SMC Call: 0x%x\n", smc_fid); 283 SMC_RET1(handle, SMC_UNK); 284 } 285 } 286 287 /******************************************************************************* 288 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI 289 * compliance when invoking bl1_smc_handler. 290 ******************************************************************************/ 291 u_register_t bl1_smc_wrapper(uint32_t smc_fid, 292 void *cookie, 293 void *handle, 294 unsigned int flags) 295 { 296 u_register_t x1, x2, x3, x4; 297 298 assert(handle != NULL); 299 300 get_smc_params_from_ctx(handle, x1, x2, x3, x4); 301 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 302 } 303