1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/cpu_data.h> 24 #include <lib/el3_runtime/pubsub_events.h> 25 #include <lib/extensions/amu.h> 26 #include <lib/extensions/brbe.h> 27 #include <lib/extensions/mpam.h> 28 #include <lib/extensions/pmuv3.h> 29 #include <lib/extensions/sme.h> 30 #include <lib/extensions/spe.h> 31 #include <lib/extensions/sve.h> 32 #include <lib/extensions/sys_reg_trace.h> 33 #include <lib/extensions/trbe.h> 34 #include <lib/extensions/trf.h> 35 #include <lib/utils.h> 36 37 #if ENABLE_FEAT_TWED 38 /* Make sure delay value fits within the range(0-15) */ 39 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 40 #endif /* ENABLE_FEAT_TWED */ 41 42 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 43 static bool has_secure_perworld_init; 44 45 static void manage_extensions_nonsecure(cpu_context_t *ctx); 46 static void manage_extensions_secure(cpu_context_t *ctx); 47 static void manage_extensions_secure_per_world(void); 48 49 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 50 { 51 u_register_t sctlr_elx, actlr_elx; 52 53 /* 54 * Initialise SCTLR_EL1 to the reset value corresponding to the target 55 * execution state setting all fields rather than relying on the hw. 56 * Some fields have architecturally UNKNOWN reset values and these are 57 * set to zero. 58 * 59 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 60 * 61 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 62 * required by PSCI specification) 63 */ 64 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 65 if (GET_RW(ep->spsr) == MODE_RW_64) { 66 sctlr_elx |= SCTLR_EL1_RES1; 67 } else { 68 /* 69 * If the target execution state is AArch32 then the following 70 * fields need to be set. 71 * 72 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 73 * instructions are not trapped to EL1. 74 * 75 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 76 * instructions are not trapped to EL1. 77 * 78 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 79 * CP15DMB, CP15DSB, and CP15ISB instructions. 80 */ 81 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 82 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 83 } 84 85 #if ERRATA_A75_764081 86 /* 87 * If workaround of errata 764081 for Cortex-A75 is used then set 88 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 89 */ 90 sctlr_elx |= SCTLR_IESB_BIT; 91 #endif 92 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 93 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 94 95 /* 96 * Base the context ACTLR_EL1 on the current value, as it is 97 * implementation defined. The context restore process will write 98 * the value from the context to the actual register and can cause 99 * problems for processor cores that don't expect certain bits to 100 * be zero. 101 */ 102 actlr_elx = read_actlr_el1(); 103 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 104 } 105 106 /****************************************************************************** 107 * This function performs initializations that are specific to SECURE state 108 * and updates the cpu context specified by 'ctx'. 109 *****************************************************************************/ 110 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 111 { 112 u_register_t scr_el3; 113 el3_state_t *state; 114 115 state = get_el3state_ctx(ctx); 116 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 117 118 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 119 /* 120 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 121 * indicated by the interrupt routing model for BL31. 122 */ 123 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 124 #endif 125 126 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 127 /* Get Memory Tagging Extension support level */ 128 unsigned int mte = get_armv8_5_mte_support(); 129 #endif 130 /* 131 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 132 * is set, or when MTE is only implemented at EL0. 133 */ 134 #if CTX_INCLUDE_MTE_REGS 135 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 136 scr_el3 |= SCR_ATA_BIT; 137 #else 138 if (mte == MTE_IMPLEMENTED_EL0) { 139 scr_el3 |= SCR_ATA_BIT; 140 } 141 #endif /* CTX_INCLUDE_MTE_REGS */ 142 143 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 144 145 /* 146 * Initialize EL1 context registers unless SPMC is running 147 * at S-EL2. 148 */ 149 #if !SPMD_SPM_AT_SEL2 150 setup_el1_context(ctx, ep); 151 #endif 152 153 manage_extensions_secure(ctx); 154 155 /** 156 * manage_extensions_secure_per_world api has to be executed once, 157 * as the registers getting initialised, maintain constant value across 158 * all the cpus for the secure world. 159 * Henceforth, this check ensures that the registers are initialised once 160 * and avoids re-initialization from multiple cores. 161 */ 162 if (!has_secure_perworld_init) { 163 manage_extensions_secure_per_world(); 164 } 165 166 } 167 168 #if ENABLE_RME 169 /****************************************************************************** 170 * This function performs initializations that are specific to REALM state 171 * and updates the cpu context specified by 'ctx'. 172 *****************************************************************************/ 173 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 174 { 175 u_register_t scr_el3; 176 el3_state_t *state; 177 178 state = get_el3state_ctx(ctx); 179 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 180 181 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 182 183 if (is_feat_csv2_2_supported()) { 184 /* Enable access to the SCXTNUM_ELx registers. */ 185 scr_el3 |= SCR_EnSCXT_BIT; 186 } 187 188 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 189 } 190 #endif /* ENABLE_RME */ 191 192 /****************************************************************************** 193 * This function performs initializations that are specific to NON-SECURE state 194 * and updates the cpu context specified by 'ctx'. 195 *****************************************************************************/ 196 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 197 { 198 u_register_t scr_el3; 199 el3_state_t *state; 200 201 state = get_el3state_ctx(ctx); 202 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 203 204 /* SCR_NS: Set the NS bit */ 205 scr_el3 |= SCR_NS_BIT; 206 207 /* Allow access to Allocation Tags when MTE is implemented. */ 208 scr_el3 |= SCR_ATA_BIT; 209 210 #if !CTX_INCLUDE_PAUTH_REGS 211 /* 212 * Pointer Authentication feature, if present, is always enabled by default 213 * for Non secure lower exception levels. We do not have an explicit 214 * flag to set it. 215 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 216 * exception levels of secure and realm worlds. 217 * 218 * To prevent the leakage between the worlds during world switch, 219 * we enable it only for the non-secure world. 220 * 221 * If the Secure/realm world wants to use pointer authentication, 222 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 223 * it will be enabled globally for all the contexts. 224 * 225 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 226 * other than EL3 227 * 228 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 229 * than EL3 230 */ 231 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 232 233 #endif /* CTX_INCLUDE_PAUTH_REGS */ 234 235 #if HANDLE_EA_EL3_FIRST_NS 236 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 237 scr_el3 |= SCR_EA_BIT; 238 #endif 239 240 #if RAS_TRAP_NS_ERR_REC_ACCESS 241 /* 242 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 243 * and RAS ERX registers from EL1 and EL2(from any security state) 244 * are trapped to EL3. 245 * Set here to trap only for NS EL1/EL2 246 * 247 */ 248 scr_el3 |= SCR_TERR_BIT; 249 #endif 250 251 if (is_feat_csv2_2_supported()) { 252 /* Enable access to the SCXTNUM_ELx registers. */ 253 scr_el3 |= SCR_EnSCXT_BIT; 254 } 255 256 #ifdef IMAGE_BL31 257 /* 258 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 259 * indicated by the interrupt routing model for BL31. 260 */ 261 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 262 #endif 263 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 264 265 /* Initialize EL1 context registers */ 266 setup_el1_context(ctx, ep); 267 268 /* Initialize EL2 context registers */ 269 #if CTX_INCLUDE_EL2_REGS 270 271 /* 272 * Initialize SCTLR_EL2 context register using Endianness value 273 * taken from the entrypoint attribute. 274 */ 275 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 276 sctlr_el2 |= SCTLR_EL2_RES1; 277 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 278 sctlr_el2); 279 280 if (is_feat_hcx_supported()) { 281 /* 282 * Initialize register HCRX_EL2 with its init value. 283 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 284 * chance that this can lead to unexpected behavior in lower 285 * ELs that have not been updated since the introduction of 286 * this feature if not properly initialized, especially when 287 * it comes to those bits that enable/disable traps. 288 */ 289 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2, 290 HCRX_EL2_INIT_VAL); 291 } 292 293 if (is_feat_fgt_supported()) { 294 /* 295 * Initialize HFG*_EL2 registers with a default value so legacy 296 * systems unaware of FEAT_FGT do not get trapped due to their lack 297 * of initialization for this feature. 298 */ 299 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGITR_EL2, 300 HFGITR_EL2_INIT_VAL); 301 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGRTR_EL2, 302 HFGRTR_EL2_INIT_VAL); 303 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HFGWTR_EL2, 304 HFGWTR_EL2_INIT_VAL); 305 } 306 #endif /* CTX_INCLUDE_EL2_REGS */ 307 308 manage_extensions_nonsecure(ctx); 309 } 310 311 /******************************************************************************* 312 * The following function performs initialization of the cpu_context 'ctx' 313 * for first use that is common to all security states, and sets the 314 * initial entrypoint state as specified by the entry_point_info structure. 315 * 316 * The EE and ST attributes are used to configure the endianness and secure 317 * timer availability for the new execution context. 318 ******************************************************************************/ 319 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 320 { 321 u_register_t scr_el3; 322 el3_state_t *state; 323 gp_regs_t *gp_regs; 324 325 state = get_el3state_ctx(ctx); 326 327 /* Clear any residual register values from the context */ 328 zeromem(ctx, sizeof(*ctx)); 329 330 /* 331 * The lower-EL context is zeroed so that no stale values leak to a world. 332 * It is assumed that an all-zero lower-EL context is good enough for it 333 * to boot correctly. However, there are very few registers where this 334 * is not true and some values need to be recreated. 335 */ 336 #if CTX_INCLUDE_EL2_REGS 337 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 338 339 /* 340 * These bits are set in the gicv3 driver. Losing them (especially the 341 * SRE bit) is problematic for all worlds. Henceforth recreate them. 342 */ 343 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 344 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 345 write_ctx_reg(el2_ctx, CTX_ICC_SRE_EL2, icc_sre_el2); 346 #endif /* CTX_INCLUDE_EL2_REGS */ 347 348 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 349 scr_el3 = SCR_RESET_VAL; 350 351 /* 352 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 353 * EL2, EL1 and EL0 are not trapped to EL3. 354 * 355 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 356 * EL2, EL1 and EL0 are not trapped to EL3. 357 * 358 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 359 * both Security states and both Execution states. 360 * 361 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 362 * Non-secure memory. 363 */ 364 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 365 366 scr_el3 |= SCR_SIF_BIT; 367 368 /* 369 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 370 * Exception level as specified by SPSR. 371 */ 372 if (GET_RW(ep->spsr) == MODE_RW_64) { 373 scr_el3 |= SCR_RW_BIT; 374 } 375 376 /* 377 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 378 * Secure timer registers to EL3, from AArch64 state only, if specified 379 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 380 * bit always behaves as 1 (i.e. secure physical timer register access 381 * is not trapped) 382 */ 383 if (EP_GET_ST(ep->h.attr) != 0U) { 384 scr_el3 |= SCR_ST_BIT; 385 } 386 387 /* 388 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 389 * SCR_EL3.HXEn. 390 */ 391 if (is_feat_hcx_supported()) { 392 scr_el3 |= SCR_HXEn_BIT; 393 } 394 395 /* 396 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 397 * registers are trapped to EL3. 398 */ 399 #if ENABLE_FEAT_RNG_TRAP 400 scr_el3 |= SCR_TRNDR_BIT; 401 #endif 402 403 #if FAULT_INJECTION_SUPPORT 404 /* Enable fault injection from lower ELs */ 405 scr_el3 |= SCR_FIEN_BIT; 406 #endif 407 408 #if CTX_INCLUDE_PAUTH_REGS 409 /* 410 * Enable Pointer Authentication globally for all the worlds. 411 * 412 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 413 * other than EL3 414 * 415 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 416 * than EL3 417 */ 418 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 419 #endif /* CTX_INCLUDE_PAUTH_REGS */ 420 421 /* 422 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 423 */ 424 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 425 scr_el3 |= SCR_TCR2EN_BIT; 426 } 427 428 /* 429 * SCR_EL3.PIEN: Enable permission indirection and overlay 430 * registers for AArch64 if present. 431 */ 432 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 433 scr_el3 |= SCR_PIEN_BIT; 434 } 435 436 /* 437 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 438 */ 439 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 440 scr_el3 |= SCR_GCSEn_BIT; 441 } 442 443 /* 444 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 445 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 446 * next mode is Hyp. 447 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 448 * same conditions as HVC instructions and when the processor supports 449 * ARMv8.6-FGT. 450 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 451 * CNTPOFF_EL2 register under the same conditions as HVC instructions 452 * and when the processor supports ECV. 453 */ 454 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 455 || ((GET_RW(ep->spsr) != MODE_RW_64) 456 && (GET_M32(ep->spsr) == MODE32_hyp))) { 457 scr_el3 |= SCR_HCE_BIT; 458 459 if (is_feat_fgt_supported()) { 460 scr_el3 |= SCR_FGTEN_BIT; 461 } 462 463 if (is_feat_ecv_supported()) { 464 scr_el3 |= SCR_ECVEN_BIT; 465 } 466 } 467 468 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 469 if (is_feat_twed_supported()) { 470 /* Set delay in SCR_EL3 */ 471 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 472 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 473 << SCR_TWEDEL_SHIFT); 474 475 /* Enable WFE delay */ 476 scr_el3 |= SCR_TWEDEn_BIT; 477 } 478 479 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 480 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 481 if (is_feat_sel2_supported()) { 482 scr_el3 |= SCR_EEL2_BIT; 483 } 484 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 485 486 if (is_feat_mpam_supported()) { 487 write_ctx_reg(get_el3state_ctx(ctx), CTX_MPAM3_EL3, \ 488 MPAM3_EL3_RESET_VAL); 489 } 490 491 /* 492 * Populate EL3 state so that we've the right context 493 * before doing ERET 494 */ 495 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 496 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 497 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 498 499 /* 500 * Store the X0-X7 value from the entrypoint into the context 501 * Use memcpy as we are in control of the layout of the structures 502 */ 503 gp_regs = get_gpregs_ctx(ctx); 504 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 505 } 506 507 /******************************************************************************* 508 * Context management library initialization routine. This library is used by 509 * runtime services to share pointers to 'cpu_context' structures for secure 510 * non-secure and realm states. Management of the structures and their associated 511 * memory is not done by the context management library e.g. the PSCI service 512 * manages the cpu context used for entry from and exit to the non-secure state. 513 * The Secure payload dispatcher service manages the context(s) corresponding to 514 * the secure state. It also uses this library to get access to the non-secure 515 * state cpu context pointers. 516 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 517 * which will be used for programming an entry into a lower EL. The same context 518 * will be used to save state upon exception entry from that EL. 519 ******************************************************************************/ 520 void __init cm_init(void) 521 { 522 /* 523 * The context management library has only global data to initialize, but 524 * that will be done when the BSS is zeroed out. 525 */ 526 } 527 528 /******************************************************************************* 529 * This is the high-level function used to initialize the cpu_context 'ctx' for 530 * first use. It performs initializations that are common to all security states 531 * and initializations specific to the security state specified in 'ep' 532 ******************************************************************************/ 533 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 534 { 535 unsigned int security_state; 536 537 assert(ctx != NULL); 538 539 /* 540 * Perform initializations that are common 541 * to all security states 542 */ 543 setup_context_common(ctx, ep); 544 545 security_state = GET_SECURITY_STATE(ep->h.attr); 546 547 /* Perform security state specific initializations */ 548 switch (security_state) { 549 case SECURE: 550 setup_secure_context(ctx, ep); 551 break; 552 #if ENABLE_RME 553 case REALM: 554 setup_realm_context(ctx, ep); 555 break; 556 #endif 557 case NON_SECURE: 558 setup_ns_context(ctx, ep); 559 break; 560 default: 561 ERROR("Invalid security state\n"); 562 panic(); 563 break; 564 } 565 } 566 567 /******************************************************************************* 568 * Enable architecture extensions for EL3 execution. This function only updates 569 * registers in-place which are expected to either never change or be 570 * overwritten by el3_exit. 571 ******************************************************************************/ 572 #if IMAGE_BL31 573 void cm_manage_extensions_el3(void) 574 { 575 if (is_feat_spe_supported()) { 576 spe_init_el3(); 577 } 578 579 if (is_feat_amu_supported()) { 580 amu_init_el3(); 581 } 582 583 if (is_feat_sme_supported()) { 584 sme_init_el3(); 585 } 586 587 if (is_feat_trbe_supported()) { 588 trbe_init_el3(); 589 } 590 591 if (is_feat_brbe_supported()) { 592 brbe_init_el3(); 593 } 594 595 if (is_feat_trf_supported()) { 596 trf_init_el3(); 597 } 598 599 pmuv3_init_el3(); 600 } 601 #endif /* IMAGE_BL31 */ 602 603 /******************************************************************************* 604 * Initialise per_world_context for Non-Secure world. 605 * This function enables the architecture extensions, which have same value 606 * across the cores for the non-secure world. 607 ******************************************************************************/ 608 #if IMAGE_BL31 609 void manage_extensions_nonsecure_per_world(void) 610 { 611 if (is_feat_sme_supported()) { 612 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 613 } 614 615 if (is_feat_sve_supported()) { 616 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 617 } 618 619 if (is_feat_amu_supported()) { 620 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 621 } 622 623 if (is_feat_sys_reg_trace_supported()) { 624 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 625 } 626 } 627 #endif /* IMAGE_BL31 */ 628 629 /******************************************************************************* 630 * Initialise per_world_context for Secure world. 631 * This function enables the architecture extensions, which have same value 632 * across the cores for the secure world. 633 ******************************************************************************/ 634 635 static void manage_extensions_secure_per_world(void) 636 { 637 #if IMAGE_BL31 638 if (is_feat_sme_supported()) { 639 640 if (ENABLE_SME_FOR_SWD) { 641 /* 642 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 643 * SME, SVE, and FPU/SIMD context properly managed. 644 */ 645 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 646 } else { 647 /* 648 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 649 * world can safely use the associated registers. 650 */ 651 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 652 } 653 } 654 if (is_feat_sve_supported()) { 655 if (ENABLE_SVE_FOR_SWD) { 656 /* 657 * Enable SVE and FPU in secure context, SPM must ensure 658 * that the SVE and FPU register contexts are properly managed. 659 */ 660 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 661 } else { 662 /* 663 * Disable SVE and FPU in secure context so non-secure world 664 * can safely use them. 665 */ 666 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 667 } 668 } 669 670 /* NS can access this but Secure shouldn't */ 671 if (is_feat_sys_reg_trace_supported()) { 672 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 673 } 674 675 has_secure_perworld_init = true; 676 #endif /* IMAGE_BL31 */ 677 } 678 679 /******************************************************************************* 680 * Enable architecture extensions on first entry to Non-secure world. 681 ******************************************************************************/ 682 static void manage_extensions_nonsecure(cpu_context_t *ctx) 683 { 684 #if IMAGE_BL31 685 if (is_feat_amu_supported()) { 686 amu_enable(ctx); 687 } 688 689 if (is_feat_sme_supported()) { 690 sme_enable(ctx); 691 } 692 693 if (is_feat_mpam_supported()) { 694 mpam_enable(ctx); 695 } 696 pmuv3_enable(ctx); 697 #endif /* IMAGE_BL31 */ 698 } 699 700 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 701 static __unused void enable_pauth_el2(void) 702 { 703 u_register_t hcr_el2 = read_hcr_el2(); 704 /* 705 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 706 * accessing key registers or using pointer authentication instructions 707 * from lower ELs. 708 */ 709 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 710 711 write_hcr_el2(hcr_el2); 712 } 713 714 /******************************************************************************* 715 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 716 * world when EL2 is empty and unused. 717 ******************************************************************************/ 718 static void manage_extensions_nonsecure_el2_unused(void) 719 { 720 #if IMAGE_BL31 721 if (is_feat_spe_supported()) { 722 spe_init_el2_unused(); 723 } 724 725 if (is_feat_amu_supported()) { 726 amu_init_el2_unused(); 727 } 728 729 if (is_feat_mpam_supported()) { 730 mpam_init_el2_unused(); 731 } 732 733 if (is_feat_trbe_supported()) { 734 trbe_init_el2_unused(); 735 } 736 737 if (is_feat_sys_reg_trace_supported()) { 738 sys_reg_trace_init_el2_unused(); 739 } 740 741 if (is_feat_trf_supported()) { 742 trf_init_el2_unused(); 743 } 744 745 pmuv3_init_el2_unused(); 746 747 if (is_feat_sve_supported()) { 748 sve_init_el2_unused(); 749 } 750 751 if (is_feat_sme_supported()) { 752 sme_init_el2_unused(); 753 } 754 755 #if ENABLE_PAUTH 756 enable_pauth_el2(); 757 #endif /* ENABLE_PAUTH */ 758 #endif /* IMAGE_BL31 */ 759 } 760 761 /******************************************************************************* 762 * Enable architecture extensions on first entry to Secure world. 763 ******************************************************************************/ 764 static void manage_extensions_secure(cpu_context_t *ctx) 765 { 766 #if IMAGE_BL31 767 if (is_feat_sme_supported()) { 768 if (ENABLE_SME_FOR_SWD) { 769 /* 770 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 771 * must ensure SME, SVE, and FPU/SIMD context properly managed. 772 */ 773 sme_init_el3(); 774 sme_enable(ctx); 775 } else { 776 /* 777 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 778 * world can safely use the associated registers. 779 */ 780 sme_disable(ctx); 781 } 782 } 783 #endif /* IMAGE_BL31 */ 784 } 785 786 /******************************************************************************* 787 * The following function initializes the cpu_context for a CPU specified by 788 * its `cpu_idx` for first use, and sets the initial entrypoint state as 789 * specified by the entry_point_info structure. 790 ******************************************************************************/ 791 void cm_init_context_by_index(unsigned int cpu_idx, 792 const entry_point_info_t *ep) 793 { 794 cpu_context_t *ctx; 795 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 796 cm_setup_context(ctx, ep); 797 } 798 799 /******************************************************************************* 800 * The following function initializes the cpu_context for the current CPU 801 * for first use, and sets the initial entrypoint state as specified by the 802 * entry_point_info structure. 803 ******************************************************************************/ 804 void cm_init_my_context(const entry_point_info_t *ep) 805 { 806 cpu_context_t *ctx; 807 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 808 cm_setup_context(ctx, ep); 809 } 810 811 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 812 static __unused void init_nonsecure_el2_unused(cpu_context_t *ctx) 813 { 814 u_register_t hcr_el2 = HCR_RESET_VAL; 815 u_register_t mdcr_el2; 816 u_register_t scr_el3; 817 818 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 819 820 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 821 if ((scr_el3 & SCR_RW_BIT) != 0U) { 822 hcr_el2 |= HCR_RW_BIT; 823 } 824 825 write_hcr_el2(hcr_el2); 826 827 /* 828 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 829 * All fields have architecturally UNKNOWN reset values. 830 */ 831 write_cptr_el2(CPTR_EL2_RESET_VAL); 832 833 /* 834 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 835 * reset and are set to zero except for field(s) listed below. 836 * 837 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 838 * Non-secure EL0 and EL1 accesses to the physical timer registers. 839 * 840 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 841 * Non-secure EL0 and EL1 accesses to the physical counter registers. 842 */ 843 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 844 845 /* 846 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 847 * UNKNOWN value. 848 */ 849 write_cntvoff_el2(0); 850 851 /* 852 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 853 * respectively. 854 */ 855 write_vpidr_el2(read_midr_el1()); 856 write_vmpidr_el2(read_mpidr_el1()); 857 858 /* 859 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 860 * 861 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 862 * translation is disabled, cache maintenance operations depend on the 863 * VMID. 864 * 865 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 866 * disabled. 867 */ 868 write_vttbr_el2(VTTBR_RESET_VAL & 869 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 870 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 871 872 /* 873 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 874 * Some fields are architecturally UNKNOWN on reset. 875 * 876 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 877 * register accesses to the Debug ROM registers are not trapped to EL2. 878 * 879 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 880 * accesses to the powerdown debug registers are not trapped to EL2. 881 * 882 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 883 * debug registers do not trap to EL2. 884 * 885 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 886 * EL2. 887 */ 888 mdcr_el2 = MDCR_EL2_RESET_VAL & 889 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 890 MDCR_EL2_TDE_BIT); 891 892 write_mdcr_el2(mdcr_el2); 893 894 /* 895 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 896 * 897 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 898 * EL1 accesses to System registers do not trap to EL2. 899 */ 900 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 901 902 /* 903 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 904 * reset. 905 * 906 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 907 * and prevent timer interrupts. 908 */ 909 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 910 911 manage_extensions_nonsecure_el2_unused(); 912 } 913 914 /******************************************************************************* 915 * Prepare the CPU system registers for first entry into realm, secure, or 916 * normal world. 917 * 918 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 919 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 920 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 921 * For all entries, the EL1 registers are initialized from the cpu_context 922 ******************************************************************************/ 923 void cm_prepare_el3_exit(uint32_t security_state) 924 { 925 u_register_t sctlr_elx, scr_el3; 926 cpu_context_t *ctx = cm_get_context(security_state); 927 928 assert(ctx != NULL); 929 930 if (security_state == NON_SECURE) { 931 uint64_t el2_implemented = el_implemented(2); 932 933 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 934 CTX_SCR_EL3); 935 936 if (((scr_el3 & SCR_HCE_BIT) != 0U) 937 || (el2_implemented != EL_IMPL_NONE)) { 938 /* 939 * If context is not being used for EL2, initialize 940 * HCRX_EL2 with its init value here. 941 */ 942 if (is_feat_hcx_supported()) { 943 write_hcrx_el2(HCRX_EL2_INIT_VAL); 944 } 945 946 /* 947 * Initialize Fine-grained trap registers introduced 948 * by FEAT_FGT so all traps are initially disabled when 949 * switching to EL2 or a lower EL, preventing undesired 950 * behavior. 951 */ 952 if (is_feat_fgt_supported()) { 953 /* 954 * Initialize HFG*_EL2 registers with a default 955 * value so legacy systems unaware of FEAT_FGT 956 * do not get trapped due to their lack of 957 * initialization for this feature. 958 */ 959 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 960 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 961 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 962 } 963 } 964 965 966 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 967 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 968 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 969 CTX_SCTLR_EL1); 970 sctlr_elx &= SCTLR_EE_BIT; 971 sctlr_elx |= SCTLR_EL2_RES1; 972 #if ERRATA_A75_764081 973 /* 974 * If workaround of errata 764081 for Cortex-A75 is used 975 * then set SCTLR_EL2.IESB to enable Implicit Error 976 * Synchronization Barrier. 977 */ 978 sctlr_elx |= SCTLR_IESB_BIT; 979 #endif 980 write_sctlr_el2(sctlr_elx); 981 } else if (el2_implemented != EL_IMPL_NONE) { 982 init_nonsecure_el2_unused(ctx); 983 } 984 } 985 986 cm_el1_sysregs_context_restore(security_state); 987 cm_set_next_eret_context(security_state); 988 } 989 990 #if CTX_INCLUDE_EL2_REGS 991 992 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 993 { 994 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2()); 995 if (is_feat_amu_supported()) { 996 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2()); 997 } 998 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2()); 999 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2()); 1000 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2()); 1001 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2()); 1002 } 1003 1004 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1005 { 1006 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2)); 1007 if (is_feat_amu_supported()) { 1008 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2)); 1009 } 1010 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2)); 1011 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2)); 1012 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2)); 1013 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2)); 1014 } 1015 1016 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1017 { 1018 u_register_t mpam_idr = read_mpamidr_el1(); 1019 1020 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2()); 1021 1022 /* 1023 * The context registers that we intend to save would be part of the 1024 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1025 */ 1026 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1027 return; 1028 } 1029 1030 /* 1031 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1032 * MPAMIDR_HAS_HCR_BIT == 1. 1033 */ 1034 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2()); 1035 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2()); 1036 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2()); 1037 1038 /* 1039 * The number of MPAMVPM registers is implementation defined, their 1040 * number is stored in the MPAMIDR_EL1 register. 1041 */ 1042 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1043 case 7: 1044 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2()); 1045 __fallthrough; 1046 case 6: 1047 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2()); 1048 __fallthrough; 1049 case 5: 1050 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2()); 1051 __fallthrough; 1052 case 4: 1053 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2()); 1054 __fallthrough; 1055 case 3: 1056 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2()); 1057 __fallthrough; 1058 case 2: 1059 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2()); 1060 __fallthrough; 1061 case 1: 1062 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2()); 1063 break; 1064 } 1065 } 1066 1067 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1068 { 1069 u_register_t mpam_idr = read_mpamidr_el1(); 1070 1071 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2)); 1072 1073 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1074 return; 1075 } 1076 1077 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2)); 1078 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2)); 1079 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2)); 1080 1081 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1082 case 7: 1083 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2)); 1084 __fallthrough; 1085 case 6: 1086 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2)); 1087 __fallthrough; 1088 case 5: 1089 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2)); 1090 __fallthrough; 1091 case 4: 1092 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2)); 1093 __fallthrough; 1094 case 3: 1095 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2)); 1096 __fallthrough; 1097 case 2: 1098 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2)); 1099 __fallthrough; 1100 case 1: 1101 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2)); 1102 break; 1103 } 1104 } 1105 1106 /* ----------------------------------------------------- 1107 * The following registers are not added: 1108 * AMEVCNTVOFF0<n>_EL2 1109 * AMEVCNTVOFF1<n>_EL2 1110 * ICH_AP0R<n>_EL2 1111 * ICH_AP1R<n>_EL2 1112 * ICH_LR<n>_EL2 1113 * ----------------------------------------------------- 1114 */ 1115 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1116 { 1117 write_ctx_reg(ctx, CTX_ACTLR_EL2, read_actlr_el2()); 1118 write_ctx_reg(ctx, CTX_AFSR0_EL2, read_afsr0_el2()); 1119 write_ctx_reg(ctx, CTX_AFSR1_EL2, read_afsr1_el2()); 1120 write_ctx_reg(ctx, CTX_AMAIR_EL2, read_amair_el2()); 1121 write_ctx_reg(ctx, CTX_CNTHCTL_EL2, read_cnthctl_el2()); 1122 write_ctx_reg(ctx, CTX_CNTVOFF_EL2, read_cntvoff_el2()); 1123 write_ctx_reg(ctx, CTX_CPTR_EL2, read_cptr_el2()); 1124 if (CTX_INCLUDE_AARCH32_REGS) { 1125 write_ctx_reg(ctx, CTX_DBGVCR32_EL2, read_dbgvcr32_el2()); 1126 } 1127 write_ctx_reg(ctx, CTX_ELR_EL2, read_elr_el2()); 1128 write_ctx_reg(ctx, CTX_ESR_EL2, read_esr_el2()); 1129 write_ctx_reg(ctx, CTX_FAR_EL2, read_far_el2()); 1130 write_ctx_reg(ctx, CTX_HACR_EL2, read_hacr_el2()); 1131 write_ctx_reg(ctx, CTX_HCR_EL2, read_hcr_el2()); 1132 write_ctx_reg(ctx, CTX_HPFAR_EL2, read_hpfar_el2()); 1133 write_ctx_reg(ctx, CTX_HSTR_EL2, read_hstr_el2()); 1134 1135 /* 1136 * Set the NS bit to be able to access the ICC_SRE_EL2 register 1137 * TODO: remove with root context 1138 */ 1139 u_register_t scr_el3 = read_scr_el3(); 1140 1141 write_scr_el3(scr_el3 | SCR_NS_BIT); 1142 isb(); 1143 write_ctx_reg(ctx, CTX_ICC_SRE_EL2, read_icc_sre_el2()); 1144 1145 write_scr_el3(scr_el3); 1146 isb(); 1147 1148 write_ctx_reg(ctx, CTX_ICH_HCR_EL2, read_ich_hcr_el2()); 1149 write_ctx_reg(ctx, CTX_ICH_VMCR_EL2, read_ich_vmcr_el2()); 1150 write_ctx_reg(ctx, CTX_MAIR_EL2, read_mair_el2()); 1151 write_ctx_reg(ctx, CTX_MDCR_EL2, read_mdcr_el2()); 1152 write_ctx_reg(ctx, CTX_SCTLR_EL2, read_sctlr_el2()); 1153 write_ctx_reg(ctx, CTX_SPSR_EL2, read_spsr_el2()); 1154 write_ctx_reg(ctx, CTX_SP_EL2, read_sp_el2()); 1155 write_ctx_reg(ctx, CTX_TCR_EL2, read_tcr_el2()); 1156 write_ctx_reg(ctx, CTX_TPIDR_EL2, read_tpidr_el2()); 1157 write_ctx_reg(ctx, CTX_TTBR0_EL2, read_ttbr0_el2()); 1158 write_ctx_reg(ctx, CTX_VBAR_EL2, read_vbar_el2()); 1159 write_ctx_reg(ctx, CTX_VMPIDR_EL2, read_vmpidr_el2()); 1160 write_ctx_reg(ctx, CTX_VPIDR_EL2, read_vpidr_el2()); 1161 write_ctx_reg(ctx, CTX_VTCR_EL2, read_vtcr_el2()); 1162 write_ctx_reg(ctx, CTX_VTTBR_EL2, read_vttbr_el2()); 1163 } 1164 1165 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1166 { 1167 write_actlr_el2(read_ctx_reg(ctx, CTX_ACTLR_EL2)); 1168 write_afsr0_el2(read_ctx_reg(ctx, CTX_AFSR0_EL2)); 1169 write_afsr1_el2(read_ctx_reg(ctx, CTX_AFSR1_EL2)); 1170 write_amair_el2(read_ctx_reg(ctx, CTX_AMAIR_EL2)); 1171 write_cnthctl_el2(read_ctx_reg(ctx, CTX_CNTHCTL_EL2)); 1172 write_cntvoff_el2(read_ctx_reg(ctx, CTX_CNTVOFF_EL2)); 1173 write_cptr_el2(read_ctx_reg(ctx, CTX_CPTR_EL2)); 1174 if (CTX_INCLUDE_AARCH32_REGS) { 1175 write_dbgvcr32_el2(read_ctx_reg(ctx, CTX_DBGVCR32_EL2)); 1176 } 1177 write_elr_el2(read_ctx_reg(ctx, CTX_ELR_EL2)); 1178 write_esr_el2(read_ctx_reg(ctx, CTX_ESR_EL2)); 1179 write_far_el2(read_ctx_reg(ctx, CTX_FAR_EL2)); 1180 write_hacr_el2(read_ctx_reg(ctx, CTX_HACR_EL2)); 1181 write_hcr_el2(read_ctx_reg(ctx, CTX_HCR_EL2)); 1182 write_hpfar_el2(read_ctx_reg(ctx, CTX_HPFAR_EL2)); 1183 write_hstr_el2(read_ctx_reg(ctx, CTX_HSTR_EL2)); 1184 1185 /* 1186 * Set the NS bit to be able to access the ICC_SRE_EL2 register 1187 * TODO: remove with root context 1188 */ 1189 u_register_t scr_el3 = read_scr_el3(); 1190 1191 write_scr_el3(scr_el3 | SCR_NS_BIT); 1192 isb(); 1193 write_icc_sre_el2(read_ctx_reg(ctx, CTX_ICC_SRE_EL2)); 1194 1195 write_scr_el3(scr_el3); 1196 isb(); 1197 1198 write_ich_hcr_el2(read_ctx_reg(ctx, CTX_ICH_HCR_EL2)); 1199 write_ich_vmcr_el2(read_ctx_reg(ctx, CTX_ICH_VMCR_EL2)); 1200 write_mair_el2(read_ctx_reg(ctx, CTX_MAIR_EL2)); 1201 write_mdcr_el2(read_ctx_reg(ctx, CTX_MDCR_EL2)); 1202 write_sctlr_el2(read_ctx_reg(ctx, CTX_SCTLR_EL2)); 1203 write_spsr_el2(read_ctx_reg(ctx, CTX_SPSR_EL2)); 1204 write_sp_el2(read_ctx_reg(ctx, CTX_SP_EL2)); 1205 write_tcr_el2(read_ctx_reg(ctx, CTX_TCR_EL2)); 1206 write_tpidr_el2(read_ctx_reg(ctx, CTX_TPIDR_EL2)); 1207 write_ttbr0_el2(read_ctx_reg(ctx, CTX_TTBR0_EL2)); 1208 write_vbar_el2(read_ctx_reg(ctx, CTX_VBAR_EL2)); 1209 write_vmpidr_el2(read_ctx_reg(ctx, CTX_VMPIDR_EL2)); 1210 write_vpidr_el2(read_ctx_reg(ctx, CTX_VPIDR_EL2)); 1211 write_vtcr_el2(read_ctx_reg(ctx, CTX_VTCR_EL2)); 1212 write_vttbr_el2(read_ctx_reg(ctx, CTX_VTTBR_EL2)); 1213 } 1214 1215 /******************************************************************************* 1216 * Save EL2 sysreg context 1217 ******************************************************************************/ 1218 void cm_el2_sysregs_context_save(uint32_t security_state) 1219 { 1220 cpu_context_t *ctx; 1221 el2_sysregs_t *el2_sysregs_ctx; 1222 1223 ctx = cm_get_context(security_state); 1224 assert(ctx != NULL); 1225 1226 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1227 1228 el2_sysregs_context_save_common(el2_sysregs_ctx); 1229 #if CTX_INCLUDE_MTE_REGS 1230 write_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2, read_tfsr_el2()); 1231 #endif 1232 if (is_feat_mpam_supported()) { 1233 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1234 } 1235 1236 if (is_feat_fgt_supported()) { 1237 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1238 } 1239 1240 if (is_feat_ecv_v2_supported()) { 1241 write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, read_cntpoff_el2()); 1242 } 1243 1244 if (is_feat_vhe_supported()) { 1245 write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, read_contextidr_el2()); 1246 write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, read_ttbr1_el2()); 1247 } 1248 1249 if (is_feat_ras_supported()) { 1250 write_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2, read_vdisr_el2()); 1251 write_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2, read_vsesr_el2()); 1252 } 1253 1254 if (is_feat_nv2_supported()) { 1255 write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, read_vncr_el2()); 1256 } 1257 1258 if (is_feat_trf_supported()) { 1259 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); 1260 } 1261 1262 if (is_feat_csv2_2_supported()) { 1263 write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, read_scxtnum_el2()); 1264 } 1265 1266 if (is_feat_hcx_supported()) { 1267 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); 1268 } 1269 if (is_feat_tcr2_supported()) { 1270 write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); 1271 } 1272 if (is_feat_sxpie_supported()) { 1273 write_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2, read_pire0_el2()); 1274 write_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2, read_pir_el2()); 1275 } 1276 if (is_feat_s2pie_supported()) { 1277 write_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2, read_s2pir_el2()); 1278 } 1279 if (is_feat_sxpoe_supported()) { 1280 write_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2, read_por_el2()); 1281 } 1282 if (is_feat_gcs_supported()) { 1283 write_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2, read_gcspr_el2()); 1284 write_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2, read_gcscr_el2()); 1285 } 1286 } 1287 1288 /******************************************************************************* 1289 * Restore EL2 sysreg context 1290 ******************************************************************************/ 1291 void cm_el2_sysregs_context_restore(uint32_t security_state) 1292 { 1293 cpu_context_t *ctx; 1294 el2_sysregs_t *el2_sysregs_ctx; 1295 1296 ctx = cm_get_context(security_state); 1297 assert(ctx != NULL); 1298 1299 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1300 1301 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1302 #if CTX_INCLUDE_MTE_REGS 1303 write_tfsr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TFSR_EL2)); 1304 #endif 1305 if (is_feat_mpam_supported()) { 1306 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1307 } 1308 1309 if (is_feat_fgt_supported()) { 1310 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1311 } 1312 1313 if (is_feat_ecv_v2_supported()) { 1314 write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2)); 1315 } 1316 1317 if (is_feat_vhe_supported()) { 1318 write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); 1319 write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); 1320 } 1321 1322 if (is_feat_ras_supported()) { 1323 write_vdisr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VDISR_EL2)); 1324 write_vsesr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VSESR_EL2)); 1325 } 1326 1327 if (is_feat_nv2_supported()) { 1328 write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); 1329 } 1330 if (is_feat_trf_supported()) { 1331 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); 1332 } 1333 1334 if (is_feat_csv2_2_supported()) { 1335 write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2)); 1336 } 1337 1338 if (is_feat_hcx_supported()) { 1339 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); 1340 } 1341 if (is_feat_tcr2_supported()) { 1342 write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); 1343 } 1344 if (is_feat_sxpie_supported()) { 1345 write_pire0_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIRE0_EL2)); 1346 write_pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_PIR_EL2)); 1347 } 1348 if (is_feat_s2pie_supported()) { 1349 write_s2pir_el2(read_ctx_reg(el2_sysregs_ctx, CTX_S2PIR_EL2)); 1350 } 1351 if (is_feat_sxpoe_supported()) { 1352 write_por_el2(read_ctx_reg(el2_sysregs_ctx, CTX_POR_EL2)); 1353 } 1354 if (is_feat_gcs_supported()) { 1355 write_gcscr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSCR_EL2)); 1356 write_gcspr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_GCSPR_EL2)); 1357 } 1358 } 1359 #endif /* CTX_INCLUDE_EL2_REGS */ 1360 1361 /******************************************************************************* 1362 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1363 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1364 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1365 * cm_prepare_el3_exit function. 1366 ******************************************************************************/ 1367 void cm_prepare_el3_exit_ns(void) 1368 { 1369 #if CTX_INCLUDE_EL2_REGS 1370 #if ENABLE_ASSERTIONS 1371 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1372 assert(ctx != NULL); 1373 1374 /* Assert that EL2 is used. */ 1375 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1376 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1377 (el_implemented(2U) != EL_IMPL_NONE)); 1378 #endif /* ENABLE_ASSERTIONS */ 1379 1380 /* Restore EL2 and EL1 sysreg contexts */ 1381 cm_el2_sysregs_context_restore(NON_SECURE); 1382 cm_el1_sysregs_context_restore(NON_SECURE); 1383 cm_set_next_eret_context(NON_SECURE); 1384 #else 1385 cm_prepare_el3_exit(NON_SECURE); 1386 #endif /* CTX_INCLUDE_EL2_REGS */ 1387 } 1388 1389 /******************************************************************************* 1390 * The next four functions are used by runtime services to save and restore 1391 * EL1 context on the 'cpu_context' structure for the specified security 1392 * state. 1393 ******************************************************************************/ 1394 void cm_el1_sysregs_context_save(uint32_t security_state) 1395 { 1396 cpu_context_t *ctx; 1397 1398 ctx = cm_get_context(security_state); 1399 assert(ctx != NULL); 1400 1401 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1402 1403 #if IMAGE_BL31 1404 if (security_state == SECURE) 1405 PUBLISH_EVENT(cm_exited_secure_world); 1406 else 1407 PUBLISH_EVENT(cm_exited_normal_world); 1408 #endif 1409 } 1410 1411 void cm_el1_sysregs_context_restore(uint32_t security_state) 1412 { 1413 cpu_context_t *ctx; 1414 1415 ctx = cm_get_context(security_state); 1416 assert(ctx != NULL); 1417 1418 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1419 1420 #if IMAGE_BL31 1421 if (security_state == SECURE) 1422 PUBLISH_EVENT(cm_entering_secure_world); 1423 else 1424 PUBLISH_EVENT(cm_entering_normal_world); 1425 #endif 1426 } 1427 1428 /******************************************************************************* 1429 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1430 * given security state with the given entrypoint 1431 ******************************************************************************/ 1432 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1433 { 1434 cpu_context_t *ctx; 1435 el3_state_t *state; 1436 1437 ctx = cm_get_context(security_state); 1438 assert(ctx != NULL); 1439 1440 /* Populate EL3 state so that ERET jumps to the correct entry */ 1441 state = get_el3state_ctx(ctx); 1442 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1443 } 1444 1445 /******************************************************************************* 1446 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1447 * pertaining to the given security state 1448 ******************************************************************************/ 1449 void cm_set_elr_spsr_el3(uint32_t security_state, 1450 uintptr_t entrypoint, uint32_t spsr) 1451 { 1452 cpu_context_t *ctx; 1453 el3_state_t *state; 1454 1455 ctx = cm_get_context(security_state); 1456 assert(ctx != NULL); 1457 1458 /* Populate EL3 state so that ERET jumps to the correct entry */ 1459 state = get_el3state_ctx(ctx); 1460 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1461 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1462 } 1463 1464 /******************************************************************************* 1465 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1466 * pertaining to the given security state using the value and bit position 1467 * specified in the parameters. It preserves all other bits. 1468 ******************************************************************************/ 1469 void cm_write_scr_el3_bit(uint32_t security_state, 1470 uint32_t bit_pos, 1471 uint32_t value) 1472 { 1473 cpu_context_t *ctx; 1474 el3_state_t *state; 1475 u_register_t scr_el3; 1476 1477 ctx = cm_get_context(security_state); 1478 assert(ctx != NULL); 1479 1480 /* Ensure that the bit position is a valid one */ 1481 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1482 1483 /* Ensure that the 'value' is only a bit wide */ 1484 assert(value <= 1U); 1485 1486 /* 1487 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1488 * and set it to its new value. 1489 */ 1490 state = get_el3state_ctx(ctx); 1491 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1492 scr_el3 &= ~(1UL << bit_pos); 1493 scr_el3 |= (u_register_t)value << bit_pos; 1494 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1495 } 1496 1497 /******************************************************************************* 1498 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1499 * given security state. 1500 ******************************************************************************/ 1501 u_register_t cm_get_scr_el3(uint32_t security_state) 1502 { 1503 cpu_context_t *ctx; 1504 el3_state_t *state; 1505 1506 ctx = cm_get_context(security_state); 1507 assert(ctx != NULL); 1508 1509 /* Populate EL3 state so that ERET jumps to the correct entry */ 1510 state = get_el3state_ctx(ctx); 1511 return read_ctx_reg(state, CTX_SCR_EL3); 1512 } 1513 1514 /******************************************************************************* 1515 * This function is used to program the context that's used for exception 1516 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1517 * the required security state 1518 ******************************************************************************/ 1519 void cm_set_next_eret_context(uint32_t security_state) 1520 { 1521 cpu_context_t *ctx; 1522 1523 ctx = cm_get_context(security_state); 1524 assert(ctx != NULL); 1525 1526 cm_set_next_context(ctx); 1527 } 1528