1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLAT_ARM_H 7 #define PLAT_ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 12 #include <drivers/arm/tzc_common.h> 13 #include <lib/bakery_lock.h> 14 #include <lib/cassert.h> 15 #include <lib/el3_runtime/cpu_data.h> 16 #include <lib/gpt_rme/gpt_rme.h> 17 #include <lib/spinlock.h> 18 #include <lib/utils_def.h> 19 #include <lib/xlat_tables/xlat_tables_compat.h> 20 21 /******************************************************************************* 22 * Forward declarations 23 ******************************************************************************/ 24 struct meminfo; 25 struct image_info; 26 struct bl_params; 27 28 typedef struct arm_tzc_regions_info { 29 unsigned long long base; 30 unsigned long long end; 31 unsigned int sec_attr; 32 unsigned int nsaid_permissions; 33 } arm_tzc_regions_info_t; 34 35 typedef struct arm_gpt_info { 36 pas_region_t *pas_region_base; 37 unsigned int pas_region_count; 38 uintptr_t l0_base; 39 uintptr_t l1_base; 40 size_t l0_size; 41 size_t l1_size; 42 gpccr_pps_e pps; 43 gpccr_pgs_e pgs; 44 } arm_gpt_info_t; 45 46 /******************************************************************************* 47 * Default mapping definition of the TrustZone Controller for ARM standard 48 * platforms. 49 * Configure: 50 * - Region 0 with no access; 51 * - Region 1 with secure access only; 52 * - the remaining DRAM regions access from the given Non-Secure masters. 53 ******************************************************************************/ 54 55 #if ENABLE_RME 56 #define ARM_TZC_RME_REGIONS_DEF \ 57 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ 58 {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ 59 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 60 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 61 /* Realm and Shared area share the same PAS */ \ 62 {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 63 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 64 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 65 PLAT_ARM_TZC_NS_DEV_ACCESS} 66 #endif 67 68 #if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) 69 #define ARM_TZC_REGIONS_DEF \ 70 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 71 TZC_REGION_S_RDWR, 0}, \ 72 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 73 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 74 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 75 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 76 {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \ 77 PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ 78 PLAT_ARM_TZC_NS_DEV_ACCESS} 79 80 #elif ENABLE_RME 81 #if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 82 MEASURED_BOOT 83 #define ARM_TZC_REGIONS_DEF \ 84 ARM_TZC_RME_REGIONS_DEF, \ 85 {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \ 86 TZC_REGION_S_RDWR, 0} 87 #else 88 #define ARM_TZC_REGIONS_DEF \ 89 ARM_TZC_RME_REGIONS_DEF 90 #endif 91 92 #else 93 #define ARM_TZC_REGIONS_DEF \ 94 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 95 TZC_REGION_S_RDWR, 0}, \ 96 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 97 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 98 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 99 PLAT_ARM_TZC_NS_DEV_ACCESS} 100 #endif 101 102 #define ARM_CASSERT_MMAP \ 103 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 104 assert_plat_arm_mmap_mismatch); \ 105 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 106 <= MAX_MMAP_REGIONS, \ 107 assert_max_mmap_regions); 108 109 void arm_setup_romlib(void); 110 111 #if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) 112 /* 113 * Use this macro to instantiate lock before it is used in below 114 * arm_lock_xxx() macros 115 */ 116 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 117 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 118 119 #if !HW_ASSISTED_COHERENCY 120 #define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) 121 #else 122 #define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock 123 #endif 124 #define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) 125 126 /* 127 * These are wrapper macros to the Coherent Memory Bakery Lock API. 128 */ 129 #define arm_lock_init() bakery_lock_init(&arm_lock) 130 #define arm_lock_get() bakery_lock_get(&arm_lock) 131 #define arm_lock_release() bakery_lock_release(&arm_lock) 132 133 #else 134 135 /* 136 * Empty macros for all other BL stages other than BL31 and BL32 137 */ 138 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 139 #define ARM_LOCK_GET_INSTANCE 0 140 #define arm_lock_init() 141 #define arm_lock_get() 142 #define arm_lock_release() 143 144 #endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ 145 146 #if ARM_RECOM_STATE_ID_ENC 147 /* 148 * Macros used to parse state information from State-ID if it is using the 149 * recommended encoding for State-ID. 150 */ 151 #define ARM_LOCAL_PSTATE_WIDTH 4 152 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 153 154 #if PSCI_OS_INIT_MODE 155 #define ARM_LAST_AT_PLVL_MASK (ARM_LOCAL_PSTATE_MASK << \ 156 (ARM_LOCAL_PSTATE_WIDTH * \ 157 (PLAT_MAX_PWR_LVL + 1))) 158 #endif /* __PSCI_OS_INIT_MODE__ */ 159 160 /* Macros to construct the composite power state */ 161 162 /* Make composite power state parameter till power level 0 */ 163 #if PSCI_EXTENDED_STATE_ID 164 165 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 166 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 167 #else 168 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 169 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 170 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 171 ((type) << PSTATE_TYPE_SHIFT)) 172 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 173 174 /* Make composite power state parameter till power level 1 */ 175 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 176 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 177 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 178 179 /* Make composite power state parameter till power level 2 */ 180 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 181 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 182 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 183 184 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 185 186 /* ARM State switch error codes */ 187 #define STATE_SW_E_PARAM (-2) 188 #define STATE_SW_E_DENIED (-3) 189 190 /* plat_get_rotpk_info() flags */ 191 #define ARM_ROTPK_REGS_ID 1 192 #define ARM_ROTPK_DEVEL_RSA_ID 2 193 #define ARM_ROTPK_DEVEL_ECDSA_ID 3 194 #define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4 195 #define ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID 5 196 197 #define ARM_USE_DEVEL_ROTPK \ 198 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ 199 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \ 200 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) || \ 201 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID) 202 203 /* IO storage utility functions */ 204 int arm_io_setup(void); 205 206 /* Set image specification in IO block policy */ 207 int arm_set_image_source(unsigned int image_id, const char *part_name, 208 uintptr_t *dev_handle, uintptr_t *image_spec); 209 void arm_set_fip_addr(uint32_t active_fw_bank_idx); 210 211 /* Security utility functions */ 212 void arm_tzc400_setup(uintptr_t tzc_base, 213 const arm_tzc_regions_info_t *tzc_regions); 214 struct tzc_dmc500_driver_data; 215 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 216 const arm_tzc_regions_info_t *tzc_regions); 217 218 /* Console utility functions */ 219 void arm_console_boot_init(void); 220 void arm_console_boot_end(void); 221 void arm_console_runtime_init(void); 222 void arm_console_runtime_end(void); 223 224 /* Systimer utility function */ 225 void arm_configure_sys_timer(void); 226 227 /* PM utility functions */ 228 int arm_validate_power_state(unsigned int power_state, 229 psci_power_state_t *req_state); 230 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 231 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 232 void arm_system_pwr_domain_save(void); 233 void arm_system_pwr_domain_resume(void); 234 int arm_psci_read_mem_protect(int *enabled); 235 int arm_nor_psci_write_mem_protect(int val); 236 void arm_nor_psci_do_static_mem_protect(void); 237 void arm_nor_psci_do_dyn_mem_protect(void); 238 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 239 240 /* Topology utility function */ 241 int arm_check_mpidr(u_register_t mpidr); 242 243 /* BL1 utility functions */ 244 void arm_bl1_early_platform_setup(void); 245 void arm_bl1_platform_setup(void); 246 void arm_bl1_plat_arch_setup(void); 247 248 /* BL2 utility functions */ 249 void arm_bl2_early_platform_setup(uintptr_t fw_config, struct meminfo *mem_layout); 250 void arm_bl2_platform_setup(void); 251 void arm_bl2_plat_arch_setup(void); 252 uint32_t arm_get_spsr_for_bl32_entry(void); 253 uint32_t arm_get_spsr_for_bl33_entry(void); 254 int arm_bl2_plat_handle_post_image_load(unsigned int image_id); 255 int arm_bl2_handle_post_image_load(unsigned int image_id); 256 struct bl_params *arm_get_next_bl_params(void); 257 258 /* BL2 at EL3 functions */ 259 void arm_bl2_el3_early_platform_setup(void); 260 void arm_bl2_el3_plat_arch_setup(void); 261 262 /* BL2U utility functions */ 263 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 264 void *plat_info); 265 void arm_bl2u_platform_setup(void); 266 void arm_bl2u_plat_arch_setup(void); 267 268 /* BL31 utility functions */ 269 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 270 uintptr_t hw_config, void *plat_params_from_bl2); 271 void arm_bl31_platform_setup(void); 272 void arm_bl31_plat_runtime_setup(void); 273 void arm_bl31_plat_arch_setup(void); 274 275 /* TSP utility functions */ 276 void arm_tsp_early_platform_setup(void); 277 278 /* SP_MIN utility functions */ 279 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 280 uintptr_t hw_config, void *plat_params_from_bl2); 281 void arm_sp_min_plat_runtime_setup(void); 282 void arm_sp_min_plat_arch_setup(void); 283 284 /* FIP TOC validity check */ 285 bool arm_io_is_toc_valid(void); 286 287 /* Utility functions for Dynamic Config */ 288 void arm_bl2_dyn_cfg_init(void); 289 void arm_bl1_set_mbedtls_heap(void); 290 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); 291 292 #if MEASURED_BOOT 293 int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size); 294 int arm_set_nt_fw_info( 295 /* 296 * Currently OP-TEE does not support reading DTBs from Secure memory 297 * and this option should be removed when feature is supported. 298 */ 299 #ifdef SPD_opteed 300 uintptr_t log_addr, 301 #endif 302 size_t log_size, uintptr_t *ns_log_addr); 303 int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size, 304 size_t log_max_size); 305 int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size, 306 size_t *log_max_size); 307 #endif /* MEASURED_BOOT */ 308 309 /* 310 * Free the memory storing initialization code only used during an images boot 311 * time so it can be reclaimed for runtime data 312 */ 313 void arm_free_init_memory(void); 314 315 /* 316 * Make the higher level translation tables read-only 317 */ 318 void arm_xlat_make_tables_readonly(void); 319 320 /* 321 * Mandatory functions required in ARM standard platforms 322 */ 323 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 324 void plat_arm_gic_driver_init(void); 325 void plat_arm_gic_init(void); 326 void plat_arm_gic_cpuif_enable(void); 327 void plat_arm_gic_cpuif_disable(void); 328 void plat_arm_gic_redistif_on(void); 329 void plat_arm_gic_redistif_off(void); 330 void plat_arm_gic_pcpu_init(void); 331 void plat_arm_gic_save(void); 332 void plat_arm_gic_resume(void); 333 void plat_arm_security_setup(void); 334 void plat_arm_pwrc_setup(void); 335 void plat_arm_interconnect_init(void); 336 void plat_arm_interconnect_enter_coherency(void); 337 void plat_arm_interconnect_exit_coherency(void); 338 void plat_arm_program_trusted_mailbox(uintptr_t address); 339 bool plat_arm_bl1_fwu_needed(void); 340 __dead2 void plat_arm_error_handler(int err); 341 __dead2 void plat_arm_system_reset(void); 342 343 /* 344 * Optional functions in ARM standard platforms 345 */ 346 void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); 347 int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, 348 unsigned int *flags); 349 int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, 350 unsigned int *flags); 351 int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, 352 unsigned int *flags); 353 int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, 354 unsigned int *flags); 355 356 #if ARM_PLAT_MT 357 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 358 #endif 359 360 /* 361 * This function is called after loading SCP_BL2 image and it is used to perform 362 * any platform-specific actions required to handle the SCP firmware. 363 */ 364 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 365 366 /* 367 * Optional functions required in ARM standard platforms 368 */ 369 void plat_arm_io_setup(void); 370 int plat_arm_get_alt_image_source( 371 unsigned int image_id, 372 uintptr_t *dev_handle, 373 uintptr_t *image_spec); 374 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 375 const mmap_region_t *plat_arm_get_mmap(void); 376 377 const arm_gpt_info_t *plat_arm_get_gpt_info(void); 378 void arm_gpt_setup(void); 379 380 /* Allow platform to override psci_pm_ops during runtime */ 381 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 382 383 /* Execution state switch in ARM platforms */ 384 int arm_execution_state_switch(unsigned int smc_fid, 385 uint32_t pc_hi, 386 uint32_t pc_lo, 387 uint32_t cookie_hi, 388 uint32_t cookie_lo, 389 void *handle); 390 391 /* Optional functions for SP_MIN */ 392 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 393 u_register_t arg2, u_register_t arg3); 394 395 /* global variables */ 396 extern plat_psci_ops_t plat_arm_psci_pm_ops; 397 extern const mmap_region_t plat_arm_mmap[]; 398 extern const unsigned int arm_pm_idle_states[]; 399 400 /* secure watchdog */ 401 void plat_arm_secure_wdt_start(void); 402 void plat_arm_secure_wdt_stop(void); 403 void plat_arm_secure_wdt_refresh(void); 404 405 /* Get SOC-ID of ARM platform */ 406 uint32_t plat_arm_get_soc_id(void); 407 408 #endif /* PLAT_ARM_H */ 409