1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <bl1/bl1.h> 15 #include <common/bl_common.h> 16 #include <common/build_message.h> 17 #include <common/debug.h> 18 #include <drivers/auth/auth_mod.h> 19 #include <drivers/auth/crypto_mod.h> 20 #include <drivers/console.h> 21 #include <lib/bootmarker_capture.h> 22 #include <lib/cpus/errata.h> 23 #include <lib/pmf/pmf.h> 24 #include <lib/utils.h> 25 #include <plat/common/platform.h> 26 #include <smccc_helpers.h> 27 #include <tools_share/uuid.h> 28 29 #include "bl1_private.h" 30 31 static void bl1_load_bl2(void); 32 33 #if ENABLE_PAUTH 34 uint64_t bl1_apiakey[2]; 35 #endif 36 37 #if ENABLE_RUNTIME_INSTRUMENTATION 38 PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID, 39 BL_TOTAL_IDS, PMF_DUMP_ENABLE) 40 #endif 41 42 /******************************************************************************* 43 * Setup function for BL1. 44 ******************************************************************************/ 45 void bl1_setup(void) 46 { 47 /* Perform early platform-specific setup */ 48 bl1_early_platform_setup(); 49 50 /* Perform late platform-specific setup */ 51 bl1_plat_arch_setup(); 52 53 #if CTX_INCLUDE_PAUTH_REGS 54 /* 55 * Assert that the ARMv8.3-PAuth registers are present or an access 56 * fault will be triggered when they are being saved or restored. 57 */ 58 assert(is_armv8_3_pauth_present()); 59 #endif /* CTX_INCLUDE_PAUTH_REGS */ 60 } 61 62 /******************************************************************************* 63 * Function to perform late architectural and platform specific initialization. 64 * It also queries the platform to load and run next BL image. Only called 65 * by the primary cpu after a cold boot. 66 ******************************************************************************/ 67 void bl1_main(void) 68 { 69 unsigned int image_id; 70 71 #if ENABLE_RUNTIME_INSTRUMENTATION 72 PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_ENTRY, PMF_CACHE_MAINT); 73 #endif 74 75 /* Announce our arrival */ 76 NOTICE(FIRMWARE_WELCOME_STR); 77 NOTICE("BL1: %s\n", build_version_string); 78 NOTICE("BL1: %s\n", build_message); 79 80 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT); 81 82 print_errata_status(); 83 84 #if ENABLE_ASSERTIONS 85 u_register_t val; 86 /* 87 * Ensure that MMU/Caches and coherency are turned on 88 */ 89 #ifdef __aarch64__ 90 val = read_sctlr_el3(); 91 #else 92 val = read_sctlr(); 93 #endif 94 assert((val & SCTLR_M_BIT) != 0); 95 assert((val & SCTLR_C_BIT) != 0); 96 assert((val & SCTLR_I_BIT) != 0); 97 /* 98 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the 99 * provided platform value 100 */ 101 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; 102 /* 103 * If CWG is zero, then no CWG information is available but we can 104 * at least check the platform value is less than the architectural 105 * maximum. 106 */ 107 if (val != 0) 108 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); 109 else 110 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); 111 #endif /* ENABLE_ASSERTIONS */ 112 113 /* Perform remaining generic architectural setup from EL3 */ 114 bl1_arch_setup(); 115 116 crypto_mod_init(); 117 118 /* Initialize authentication module */ 119 auth_mod_init(); 120 121 /* Initialize the measured boot */ 122 bl1_plat_mboot_init(); 123 124 /* Perform platform setup in BL1. */ 125 bl1_platform_setup(); 126 127 #if ENABLE_PAUTH 128 /* Store APIAKey_EL1 key */ 129 bl1_apiakey[0] = read_apiakeylo_el1(); 130 bl1_apiakey[1] = read_apiakeyhi_el1(); 131 #endif /* ENABLE_PAUTH */ 132 133 /* Get the image id of next image to load and run. */ 134 image_id = bl1_plat_get_next_image_id(); 135 136 /* 137 * We currently interpret any image id other than 138 * BL2_IMAGE_ID as the start of firmware update. 139 */ 140 if (image_id == BL2_IMAGE_ID) 141 bl1_load_bl2(); 142 else 143 NOTICE("BL1-FWU: *******FWU Process Started*******\n"); 144 145 /* Teardown the measured boot driver */ 146 bl1_plat_mboot_finish(); 147 148 bl1_prepare_next_image(image_id); 149 150 #if ENABLE_RUNTIME_INSTRUMENTATION 151 PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_EXIT, PMF_CACHE_MAINT); 152 #endif 153 154 console_flush(); 155 } 156 157 /******************************************************************************* 158 * This function locates and loads the BL2 raw binary image in the trusted SRAM. 159 * Called by the primary cpu after a cold boot. 160 * TODO: Add support for alternative image load mechanism e.g using virtio/elf 161 * loader etc. 162 ******************************************************************************/ 163 static void bl1_load_bl2(void) 164 { 165 image_desc_t *desc; 166 image_info_t *info; 167 int err; 168 169 /* Get the image descriptor */ 170 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); 171 assert(desc != NULL); 172 173 /* Get the image info */ 174 info = &desc->image_info; 175 INFO("BL1: Loading BL2\n"); 176 177 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID); 178 if (err != 0) { 179 ERROR("Failure in pre image load handling of BL2 (%d)\n", err); 180 plat_error_handler(err); 181 } 182 183 err = load_auth_image(BL2_IMAGE_ID, info); 184 if (err != 0) { 185 ERROR("Failed to load BL2 firmware.\n"); 186 plat_error_handler(err); 187 } 188 189 /* Allow platform to handle image information. */ 190 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID); 191 if (err != 0) { 192 ERROR("Failure in post image load handling of BL2 (%d)\n", err); 193 plat_error_handler(err); 194 } 195 196 NOTICE("BL1: Booting BL2\n"); 197 } 198 199 /******************************************************************************* 200 * Function called just before handing over to the next BL to inform the user 201 * about the boot progress. In debug mode, also print details about the BL 202 * image's execution context. 203 ******************************************************************************/ 204 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info) 205 { 206 #ifdef __aarch64__ 207 NOTICE("BL1: Booting BL31\n"); 208 #else 209 NOTICE("BL1: Booting BL32\n"); 210 #endif /* __aarch64__ */ 211 print_entry_point_info(bl_ep_info); 212 } 213 214 #if SPIN_ON_BL1_EXIT 215 void print_debug_loop_message(void) 216 { 217 NOTICE("BL1: Debug loop, spinning forever\n"); 218 NOTICE("BL1: Please connect the debugger to continue\n"); 219 } 220 #endif 221 222 /******************************************************************************* 223 * Top level handler for servicing BL1 SMCs. 224 ******************************************************************************/ 225 u_register_t bl1_smc_handler(unsigned int smc_fid, 226 u_register_t x1, 227 u_register_t x2, 228 u_register_t x3, 229 u_register_t x4, 230 void *cookie, 231 void *handle, 232 unsigned int flags) 233 { 234 /* BL1 Service UUID */ 235 DEFINE_SVC_UUID2(bl1_svc_uid, 236 U(0xd46739fd), 0xcb72, 0x9a4d, 0xb5, 0x75, 237 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a); 238 239 240 #if TRUSTED_BOARD_BOOT 241 /* 242 * Dispatch FWU calls to FWU SMC handler and return its return 243 * value 244 */ 245 if (is_fwu_fid(smc_fid)) { 246 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie, 247 handle, flags); 248 } 249 #endif 250 251 switch (smc_fid) { 252 case BL1_SMC_CALL_COUNT: 253 SMC_RET1(handle, BL1_NUM_SMC_CALLS); 254 255 case BL1_SMC_UID: 256 SMC_UUID_RET(handle, bl1_svc_uid); 257 258 case BL1_SMC_VERSION: 259 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER); 260 261 default: 262 WARN("Unimplemented BL1 SMC Call: 0x%x\n", smc_fid); 263 SMC_RET1(handle, SMC_UNK); 264 } 265 } 266 267 /******************************************************************************* 268 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI 269 * compliance when invoking bl1_smc_handler. 270 ******************************************************************************/ 271 u_register_t bl1_smc_wrapper(uint32_t smc_fid, 272 void *cookie, 273 void *handle, 274 unsigned int flags) 275 { 276 u_register_t x1, x2, x3, x4; 277 278 assert(handle != NULL); 279 280 get_smc_params_from_ctx(handle, x1, x2, x3, x4); 281 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 282 } 283