1 /* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <drivers/console.h> 14 #include <lib/debugfs.h> 15 #include <lib/extensions/ras.h> 16 #include <lib/gpt_rme/gpt_rme.h> 17 #include <lib/mmio.h> 18 #include <lib/xlat_tables/xlat_tables_compat.h> 19 #include <plat/arm/common/plat_arm.h> 20 #include <plat/common/platform.h> 21 #include <platform_def.h> 22 23 /* 24 * Placeholder variables for copying the arguments that have been passed to 25 * BL31 from BL2. 26 */ 27 static entry_point_info_t bl32_image_ep_info; 28 static entry_point_info_t bl33_image_ep_info; 29 #if ENABLE_RME 30 static entry_point_info_t rmm_image_ep_info; 31 #endif 32 33 #if !RESET_TO_BL31 34 /* 35 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page 36 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 37 */ 38 CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); 39 #endif 40 41 /* Weak definitions may be overridden in specific ARM standard platform */ 42 #pragma weak bl31_early_platform_setup2 43 #pragma weak bl31_platform_setup 44 #pragma weak bl31_plat_arch_setup 45 #pragma weak bl31_plat_get_next_image_ep_info 46 #pragma weak bl31_plat_runtime_setup 47 48 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 49 BL31_START, \ 50 BL31_END - BL31_START, \ 51 MT_MEMORY | MT_RW | EL3_PAS) 52 #if RECLAIM_INIT_CODE 53 IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE); 54 IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED); 55 IMPORT_SYM(unsigned long, __STACKS_END__, BL_STACKS_END_UNALIGNED); 56 57 #define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \ 58 ~(PAGE_SIZE - 1)) 59 #define BL_STACKS_END ((BL_STACKS_END_UNALIGNED + PAGE_SIZE - 1) & \ 60 ~(PAGE_SIZE - 1)) 61 62 #define MAP_BL_INIT_CODE MAP_REGION_FLAT( \ 63 BL_INIT_CODE_BASE, \ 64 BL_INIT_CODE_END \ 65 - BL_INIT_CODE_BASE, \ 66 MT_CODE | EL3_PAS) 67 #endif 68 69 #if SEPARATE_NOBITS_REGION 70 #define MAP_BL31_NOBITS MAP_REGION_FLAT( \ 71 BL31_NOBITS_BASE, \ 72 BL31_NOBITS_LIMIT \ 73 - BL31_NOBITS_BASE, \ 74 MT_MEMORY | MT_RW | EL3_PAS) 75 76 #endif 77 /******************************************************************************* 78 * Return a pointer to the 'entry_point_info' structure of the next image for the 79 * security state specified. BL33 corresponds to the non-secure image type 80 * while BL32 corresponds to the secure image type. A NULL pointer is returned 81 * if the image does not exist. 82 ******************************************************************************/ 83 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 84 { 85 entry_point_info_t *next_image_info; 86 87 assert(sec_state_is_valid(type)); 88 if (type == NON_SECURE) { 89 next_image_info = &bl33_image_ep_info; 90 } 91 #if ENABLE_RME 92 else if (type == REALM) { 93 next_image_info = &rmm_image_ep_info; 94 } 95 #endif 96 else { 97 next_image_info = &bl32_image_ep_info; 98 } 99 100 /* 101 * None of the images on the ARM development platforms can have 0x0 102 * as the entrypoint 103 */ 104 if (next_image_info->pc) 105 return next_image_info; 106 else 107 return NULL; 108 } 109 110 /******************************************************************************* 111 * Perform any BL31 early platform setup common to ARM standard platforms. 112 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 113 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 114 * done before the MMU is initialized so that the memory layout can be used 115 * while creating page tables. BL2 has flushed this information to memory, so 116 * we are guaranteed to pick up good data. 117 ******************************************************************************/ 118 void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 119 uintptr_t hw_config, void *plat_params_from_bl2) 120 { 121 /* Initialize the console to provide early debug support */ 122 arm_console_boot_init(); 123 124 #if RESET_TO_BL31 125 /* There are no parameters from BL2 if BL31 is a reset vector */ 126 assert(from_bl2 == NULL); 127 assert(plat_params_from_bl2 == NULL); 128 129 # ifdef BL32_BASE 130 /* Populate entry point information for BL32 */ 131 SET_PARAM_HEAD(&bl32_image_ep_info, 132 PARAM_EP, 133 VERSION_1, 134 0); 135 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 136 bl32_image_ep_info.pc = BL32_BASE; 137 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 138 139 #if defined(SPD_spmd) 140 /* SPM (hafnium in secure world) expects SPM Core manifest base address 141 * in x0, which in !RESET_TO_BL31 case loaded after base of non shared 142 * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non 143 * shared SRAM is allocated to BL31, so to avoid overwriting of manifest 144 * keep it in the last page. 145 */ 146 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + 147 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE; 148 #endif 149 150 # endif /* BL32_BASE */ 151 152 /* Populate entry point information for BL33 */ 153 SET_PARAM_HEAD(&bl33_image_ep_info, 154 PARAM_EP, 155 VERSION_1, 156 0); 157 /* 158 * Tell BL31 where the non-trusted software image 159 * is located and the entry state information 160 */ 161 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 162 163 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 164 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 165 166 #if ENABLE_RME 167 /* 168 * Populate entry point information for RMM. 169 * Only PC needs to be set as other fields are determined by RMMD. 170 */ 171 rmm_image_ep_info.pc = RMM_BASE; 172 #endif /* ENABLE_RME */ 173 174 #else /* RESET_TO_BL31 */ 175 176 /* 177 * In debug builds, we pass a special value in 'plat_params_from_bl2' 178 * to verify platform parameters from BL2 to BL31. 179 * In release builds, it's not used. 180 */ 181 assert(((unsigned long long)plat_params_from_bl2) == 182 ARM_BL31_PLAT_PARAM_VAL); 183 184 /* 185 * Check params passed from BL2 should not be NULL, 186 */ 187 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 188 assert(params_from_bl2 != NULL); 189 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 190 assert(params_from_bl2->h.version >= VERSION_2); 191 192 bl_params_node_t *bl_params = params_from_bl2->head; 193 194 /* 195 * Copy BL33, BL32 and RMM (if present), entry point information. 196 * They are stored in Secure RAM, in BL2's address space. 197 */ 198 while (bl_params != NULL) { 199 if (bl_params->image_id == BL32_IMAGE_ID) { 200 bl32_image_ep_info = *bl_params->ep_info; 201 } 202 #if ENABLE_RME 203 else if (bl_params->image_id == RMM_IMAGE_ID) { 204 rmm_image_ep_info = *bl_params->ep_info; 205 } 206 #endif 207 else if (bl_params->image_id == BL33_IMAGE_ID) { 208 bl33_image_ep_info = *bl_params->ep_info; 209 } 210 211 bl_params = bl_params->next_params_info; 212 } 213 214 if (bl33_image_ep_info.pc == 0U) 215 panic(); 216 #if ENABLE_RME 217 if (rmm_image_ep_info.pc == 0U) 218 panic(); 219 #endif 220 #endif /* RESET_TO_BL31 */ 221 222 # if ARM_LINUX_KERNEL_AS_BL33 223 /* 224 * According to the file ``Documentation/arm64/booting.txt`` of the 225 * Linux kernel tree, Linux expects the physical address of the device 226 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and 227 * must be 0. 228 * Repurpose the option to load Hafnium hypervisor in the normal world. 229 * It expects its manifest address in x0. This is essentially the linux 230 * dts (passed to the primary VM) by adding 'hypervisor' and chosen 231 * nodes specifying the Hypervisor configuration. 232 */ 233 #if RESET_TO_BL31 234 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; 235 #else 236 bl33_image_ep_info.args.arg0 = (u_register_t)hw_config; 237 #endif 238 bl33_image_ep_info.args.arg1 = 0U; 239 bl33_image_ep_info.args.arg2 = 0U; 240 bl33_image_ep_info.args.arg3 = 0U; 241 # endif 242 } 243 244 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 245 u_register_t arg2, u_register_t arg3) 246 { 247 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 248 249 /* 250 * Initialize Interconnect for this cluster during cold boot. 251 * No need for locks as no other CPU is active. 252 */ 253 plat_arm_interconnect_init(); 254 255 /* 256 * Enable Interconnect coherency for the primary CPU's cluster. 257 * Earlier bootloader stages might already do this (e.g. Trusted 258 * Firmware's BL1 does it) but we can't assume so. There is no harm in 259 * executing this code twice anyway. 260 * Platform specific PSCI code will enable coherency for other 261 * clusters. 262 */ 263 plat_arm_interconnect_enter_coherency(); 264 } 265 266 /******************************************************************************* 267 * Perform any BL31 platform setup common to ARM standard platforms 268 ******************************************************************************/ 269 void arm_bl31_platform_setup(void) 270 { 271 /* Initialize the GIC driver, cpu and distributor interfaces */ 272 plat_arm_gic_driver_init(); 273 plat_arm_gic_init(); 274 275 #if RESET_TO_BL31 276 /* 277 * Do initial security configuration to allow DRAM/device access 278 * (if earlier BL has not already done so). 279 */ 280 plat_arm_security_setup(); 281 282 #if defined(PLAT_ARM_MEM_PROT_ADDR) 283 arm_nor_psci_do_dyn_mem_protect(); 284 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 285 286 #endif /* RESET_TO_BL31 */ 287 288 /* Enable and initialize the System level generic timer */ 289 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 290 CNTCR_FCREQ(0U) | CNTCR_EN); 291 292 /* Allow access to the System counter timer module */ 293 arm_configure_sys_timer(); 294 295 /* Initialize power controller before setting up topology */ 296 plat_arm_pwrc_setup(); 297 298 #if ENABLE_FEAT_RAS && FFH_SUPPORT 299 ras_init(); 300 #endif 301 302 #if USE_DEBUGFS 303 debugfs_init(); 304 #endif /* USE_DEBUGFS */ 305 } 306 307 /******************************************************************************* 308 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM 309 * standard platforms 310 * Perform BL31 platform setup 311 ******************************************************************************/ 312 void arm_bl31_plat_runtime_setup(void) 313 { 314 console_switch_state(CONSOLE_FLAG_RUNTIME); 315 316 /* Initialize the runtime console */ 317 arm_console_runtime_init(); 318 319 #if RECLAIM_INIT_CODE 320 arm_free_init_memory(); 321 #endif 322 323 #if PLAT_RO_XLAT_TABLES 324 arm_xlat_make_tables_readonly(); 325 #endif 326 } 327 328 #if RECLAIM_INIT_CODE 329 /* 330 * Make memory for image boot time code RW to reclaim it as stack for the 331 * secondary cores, or RO where it cannot be reclaimed: 332 * 333 * |-------- INIT SECTION --------| 334 * ----------------------------------------- 335 * | CORE 0 | CORE 1 | CORE 2 | EXTRA | 336 * | STACK | STACK | STACK | SPACE | 337 * ----------------------------------------- 338 * <-------------------> <------> 339 * MAKE RW AND XN MAKE 340 * FOR STACKS RO AND XN 341 */ 342 void arm_free_init_memory(void) 343 { 344 int ret = 0; 345 346 if (BL_STACKS_END < BL_INIT_CODE_END) { 347 /* Reclaim some of the init section as stack if possible. */ 348 if (BL_INIT_CODE_BASE < BL_STACKS_END) { 349 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 350 BL_STACKS_END - BL_INIT_CODE_BASE, 351 MT_RW_DATA); 352 } 353 /* Make the rest of the init section read-only. */ 354 ret |= xlat_change_mem_attributes(BL_STACKS_END, 355 BL_INIT_CODE_END - BL_STACKS_END, 356 MT_RO_DATA); 357 } else { 358 /* The stacks cover the init section, so reclaim it all. */ 359 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE, 360 BL_INIT_CODE_END - BL_INIT_CODE_BASE, 361 MT_RW_DATA); 362 } 363 364 if (ret != 0) { 365 ERROR("Could not reclaim initialization code"); 366 panic(); 367 } 368 } 369 #endif 370 371 void __init bl31_platform_setup(void) 372 { 373 arm_bl31_platform_setup(); 374 } 375 376 void bl31_plat_runtime_setup(void) 377 { 378 arm_bl31_plat_runtime_setup(); 379 } 380 381 /******************************************************************************* 382 * Perform the very early platform specific architectural setup shared between 383 * ARM standard platforms. This only does basic initialization. Later 384 * architectural setup (bl31_arch_setup()) does not do anything platform 385 * specific. 386 ******************************************************************************/ 387 void __init arm_bl31_plat_arch_setup(void) 388 { 389 const mmap_region_t bl_regions[] = { 390 MAP_BL31_TOTAL, 391 #if ENABLE_RME 392 ARM_MAP_L0_GPT_REGION, 393 #endif 394 #if RECLAIM_INIT_CODE 395 MAP_BL_INIT_CODE, 396 #endif 397 #if SEPARATE_NOBITS_REGION 398 MAP_BL31_NOBITS, 399 #endif 400 ARM_MAP_BL_RO, 401 #if USE_ROMLIB 402 ARM_MAP_ROMLIB_CODE, 403 ARM_MAP_ROMLIB_DATA, 404 #endif 405 #if USE_COHERENT_MEM 406 ARM_MAP_BL_COHERENT_RAM, 407 #endif 408 {0} 409 }; 410 411 setup_page_tables(bl_regions, plat_arm_get_mmap()); 412 413 enable_mmu_el3(0); 414 415 #if ENABLE_RME 416 /* 417 * Initialise Granule Protection library and enable GPC for the primary 418 * processor. The tables have already been initialized by a previous BL 419 * stage, so there is no need to provide any PAS here. This function 420 * sets up pointers to those tables. 421 */ 422 if (gpt_runtime_init() < 0) { 423 ERROR("gpt_runtime_init() failed!\n"); 424 panic(); 425 } 426 #endif /* ENABLE_RME */ 427 428 arm_setup_romlib(); 429 } 430 431 void __init bl31_plat_arch_setup(void) 432 { 433 arm_bl31_plat_arch_setup(); 434 } 435