1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <errno.h> 11 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 #include <plat/common/platform.h> 18 #include <plat_arm.h> 19 #include <plat_console.h> 20 21 #include <plat_fdt.h> 22 #include <plat_private.h> 23 #include <plat_startup.h> 24 #include <pm_api_sys.h> 25 #include <pm_client.h> 26 #include <pm_ipi.h> 27 #include <versal_net_def.h> 28 29 static entry_point_info_t bl32_image_ep_info; 30 static entry_point_info_t bl33_image_ep_info; 31 32 /* 33 * Return a pointer to the 'entry_point_info' structure of the next image for 34 * the security state specified. BL33 corresponds to the non-secure image type 35 * while BL32 corresponds to the secure image type. A NULL pointer is returned 36 * if the image does not exist. 37 */ 38 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 39 { 40 assert(sec_state_is_valid(type)); 41 42 if (type == NON_SECURE) { 43 return &bl33_image_ep_info; 44 } 45 46 return &bl32_image_ep_info; 47 } 48 49 /* 50 * Set the build time defaults,if we can't find any config data. 51 */ 52 static inline void bl31_set_default_config(void) 53 { 54 bl32_image_ep_info.pc = BL32_BASE; 55 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); 56 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 57 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, 58 DISABLE_ALL_EXCEPTIONS); 59 } 60 61 /* 62 * Perform any BL31 specific platform actions. Here is an opportunity to copy 63 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 64 * are lost (potentially). This needs to be done before the MMU is initialized 65 * so that the memory layout can be used while creating page tables. 66 */ 67 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 68 u_register_t arg2, u_register_t arg3) 69 { 70 #if !(TFA_NO_PM) 71 uint64_t tfa_handoff_addr, buff[HANDOFF_PARAMS_MAX_SIZE] = {0}; 72 uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE; 73 enum pm_ret_status ret_status; 74 #endif /* !(TFA_NO_PM) */ 75 76 board_detection(); 77 78 switch (platform_id) { 79 case VERSAL_NET_SPP: 80 cpu_clock = 1000000; 81 break; 82 case VERSAL_NET_EMU: 83 cpu_clock = 3660000; 84 break; 85 case VERSAL_NET_QEMU: 86 /* Random values now */ 87 cpu_clock = 100000000; 88 break; 89 case VERSAL_NET_SILICON: 90 cpu_clock = 100000000; 91 break; 92 default: 93 panic(); 94 } 95 96 setup_console(); 97 98 NOTICE("TF-A running on %s %d.%d\n", board_name_decode(), 99 platform_version / 10U, platform_version % 10U); 100 101 /* Initialize the platform config for future decision making */ 102 versal_net_config_setup(); 103 104 /* 105 * Do initial security configuration to allow DRAM/device access. On 106 * Base VERSAL_NET only DRAM security is programmable (via TrustZone), but 107 * other platforms might have more programmable security devices 108 * present. 109 */ 110 111 /* Populate common information for BL32 and BL33 */ 112 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 113 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 114 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); 115 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 116 #if !(TFA_NO_PM) 117 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS, 118 (uintptr_t)buff >> 32U, (uintptr_t)buff, max_size); 119 120 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); 121 if (ret_status == PM_RET_SUCCESS) { 122 enum xbl_handoff xbl_ret; 123 124 tfa_handoff_addr = (uintptr_t)&buff; 125 126 xbl_ret = xbl_handover(&bl32_image_ep_info, &bl33_image_ep_info, 127 tfa_handoff_addr); 128 if (xbl_ret != XBL_HANDOFF_SUCCESS) { 129 ERROR("BL31: PLM to TF-A handover failed %u\n", xbl_ret); 130 panic(); 131 } 132 133 INFO("BL31: PLM to TF-A handover success\n"); 134 135 /* 136 * The BL32 load address is indicated as 0x0 in the handoff 137 * parameters, which is different from the default/user-provided 138 * load address of 0x60000000 but the flags are correctly 139 * configured. Consequently, in this scenario, set the PC 140 * to the requested BL32_BASE address. 141 */ 142 143 /* TODO: Remove the following check once this is fixed from PLM */ 144 if (bl32_image_ep_info.pc == 0 && bl32_image_ep_info.spsr != 0) { 145 bl32_image_ep_info.pc = (uintptr_t)BL32_BASE; 146 } 147 } else { 148 INFO("BL31: setting up default configs\n"); 149 150 bl31_set_default_config(); 151 } 152 #else 153 bl31_set_default_config(); 154 #endif /* !(TFA_NO_PM) */ 155 156 NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); 157 NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); 158 } 159 160 static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3]; 161 162 int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler) 163 { 164 static uint32_t index; 165 uint32_t i; 166 167 /* Validate 'handler' and 'id' parameters */ 168 if (handler == NULL || index >= MAX_INTR_EL3) { 169 return -EINVAL; 170 } 171 172 /* Check if a handler has already been registered */ 173 for (i = 0; i < index; i++) { 174 if (id == type_el3_interrupt_table[i].id) { 175 return -EALREADY; 176 } 177 } 178 179 type_el3_interrupt_table[index].id = id; 180 type_el3_interrupt_table[index].handler = handler; 181 182 index++; 183 184 return 0; 185 } 186 187 static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags, 188 void *handle, void *cookie) 189 { 190 uint32_t intr_id; 191 uint32_t i; 192 interrupt_type_handler_t handler = NULL; 193 194 intr_id = plat_ic_get_pending_interrupt_id(); 195 196 for (i = 0; i < MAX_INTR_EL3; i++) { 197 if (intr_id == type_el3_interrupt_table[i].id) { 198 handler = type_el3_interrupt_table[i].handler; 199 } 200 } 201 202 if (handler != NULL) { 203 handler(intr_id, flags, handle, cookie); 204 } 205 206 return 0; 207 } 208 209 void bl31_platform_setup(void) 210 { 211 prepare_dtb(); 212 213 /* Initialize the gic cpu and distributor interfaces */ 214 plat_versal_net_gic_driver_init(); 215 plat_versal_net_gic_init(); 216 } 217 218 void bl31_plat_runtime_setup(void) 219 { 220 uint64_t flags = 0; 221 int32_t rc; 222 223 set_interrupt_rm_flag(flags, NON_SECURE); 224 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 225 rdo_el3_interrupt_handler, flags); 226 if (rc != 0) { 227 panic(); 228 } 229 230 console_switch_state(CONSOLE_FLAG_RUNTIME); 231 } 232 233 /* 234 * Perform the very early platform specific architectural setup here. 235 */ 236 void bl31_plat_arch_setup(void) 237 { 238 const mmap_region_t bl_regions[] = { 239 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 240 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE, 241 MT_MEMORY | MT_RW | MT_NS), 242 #endif 243 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, 244 MT_MEMORY | MT_RW | MT_SECURE), 245 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, 246 MT_CODE | MT_SECURE), 247 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, 248 MT_RO_DATA | MT_SECURE), 249 {0} 250 }; 251 252 setup_page_tables(bl_regions, plat_get_mmap()); 253 enable_mmu(0); 254 } 255