Switch AARCH32/AARCH64 to __aarch64__

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the cod

Switch AARCH32/AARCH64 to __aarch64__

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)

Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: Julius Werner <jwerner@chromium.org>

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bl2_el3: clean up linker script

This linker script is so unreadable due to sprinkled #ifdef.

Direct read-only data to 'ROM' and read-write data to 'RAM'.

Both go to the same memory device when BL2

bl2_el3: clean up linker script

This linker script is so unreadable due to sprinkled #ifdef.

Direct read-only data to 'ROM' and read-write data to 'RAM'.

Both go to the same memory device when BL2_IN_XIP_MEM is disabled.

Change-Id: Ieeac3f1a4e05e9e8599de2ec84260819c70f361e
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Add support for Branch Target Identification

This patch adds the functionality needed for platforms to provide
Branch Target Identification (BTI) extension, introduced to AArch64
in Armv8.5-A by add

Add support for Branch Target Identification

This patch adds the functionality needed for platforms to provide
Branch Target Identification (BTI) extension, introduced to AArch64
in Armv8.5-A by adding BTI instruction used to mark valid targets
for indirect branches. The patch sets new GP bit [50] to the stage 1
Translation Table Block and Page entries to denote guarded EL3 code
pages which will cause processor to trap instructions in protected
pages trying to perform an indirect branch to any instruction other
than BTI.
BTI feature is selected by BRANCH_PROTECTION option which supersedes
the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication
and is disabled by default. Enabling BTI requires compiler support
and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0.
The assembly macros and helpers are modified to accommodate the BTI
instruction.
This is an experimental feature.
Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3
is now made as an internal flag and BRANCH_PROTECTION flag should be
used instead to enable Pointer Authentication.
Note. USE_LIBROM=1 option is currently not supported.

Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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Merge pull request #1878 from jts-arm/sctlr

Apply stricter speculative load restriction

bl2-el3: Fix exit to bl32 by ensuring a more complete write to SPSR

Prior to entry into BL32 we set the SPSR by way of msr spsr, r1.
This unfortunately only writes the bits f->[31:24] and c->[7:0].

bl2-el3: Fix exit to bl32 by ensuring a more complete write to SPSR

Prior to entry into BL32 we set the SPSR by way of msr spsr, r1.
This unfortunately only writes the bits f->[31:24] and c->[7:0].

This patch updates the bl2 exit path to write the x->[15:8] and c->[7:0]
fields of the SPSR. For the purposes of initial setup of the SPSR the x and
c fields should be sufficient and importantly will capture the necessary
lower-order control bits that f:c alone do not.

This is important to do to ensure the SPSR is set to the mode the platform
intends prior to performing an eret.

Fixes: b1d27b484f41 ("bl2-el3: Add BL2_EL3 image")

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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Apply stricter speculative load restriction

The SCTLR.DSSBS bit is zero by default thus disabling speculative loads.
However, we also explicitly set it to zero for BL2 and TSP images when
each image

Apply stricter speculative load restriction

The SCTLR.DSSBS bit is zero by default thus disabling speculative loads.
However, we also explicitly set it to zero for BL2 and TSP images when
each image initialises its context. This is done to ensure that the
image environment is initialised in a safe state, regardless of the
reset value of the bit.

Change-Id: If25a8396641edb640f7f298b8d3309d5cba3cd79
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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BL2_AT_EL3: Enable pointer authentication support

The size increase after enabling options related to ARMv8.3-PAuth is:

+----------------------------+-------+-------+-------+--------+
|

BL2_AT_EL3: Enable pointer authentication support

The size increase after enabling options related to ARMv8.3-PAuth is:

+----------------------------+-------+-------+-------+--------+
| | text | bss | data | rodata |
+----------------------------+-------+-------+-------+--------+
| CTX_INCLUDE_PAUTH_REGS = 1 | +44 | +0 | +0 | +0 |
| | 0.2% | | | |
+----------------------------+-------+-------+-------+--------+
| ENABLE_PAUTH = 1 | +712 | +0 | +16 | +0 |
| | 3.1% | | 0.9% | |
+----------------------------+-------+-------+-------+--------+

The results are valid for the following build configuration:

make PLAT=fvp SPD=tspd DEBUG=1 \
BL2_AT_EL3=1 \
CTX_INCLUDE_PAUTH_REGS=1 \
ENABLE_PAUTH=1

Change-Id: I1c0616e7dea30962a92b4fd113428bc30a018320
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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BL2: Enable pointer authentication support

The size increase after enabling options related to ARMv8.3-PAuth is:

+----------------------------+-------+-------+-------+--------+
|

BL2: Enable pointer authentication support

The size increase after enabling options related to ARMv8.3-PAuth is:

+----------------------------+-------+-------+-------+--------+
| | text | bss | data | rodata |
+----------------------------+-------+-------+-------+--------+
| CTX_INCLUDE_PAUTH_REGS = 1 | +40 | +0 | +0 | +0 |
| | 0.2% | | | |
+----------------------------+-------+-------+-------+--------+
| ENABLE_PAUTH = 1 | +664 | +0 | +16 | +0 |
| | 3.1% | | 0.9% | |
+----------------------------+-------+-------+-------+--------+

Results calculated with the following build configuration:

make PLAT=fvp SPD=tspd DEBUG=1 \
SDEI_SUPPORT=1 \
EL3_EXCEPTION_HANDLING=1 \
TSP_NS_INTR_ASYNC_PREEMPT=1 \
CTX_INCLUDE_PAUTH_REGS=1 \
ENABLE_PAUTH=1

The changes for BL2_AT_EL3 aren't done in this commit.

Change-Id: I8c803b40c7160525a06173bc6cdca21c4505837d
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Move BL1 and BL2 private defines to bl_common.h

The definitions in bl1/bl1_private.h and bl2/bl2_private.h are useful for
platforms that may need to access them.

Change-Id: Ifd1880f855ddafcb3bfcaf1

Move BL1 and BL2 private defines to bl_common.h

The definitions in bl1/bl1_private.h and bl2/bl2_private.h are useful for
platforms that may need to access them.

Change-Id: Ifd1880f855ddafcb3bfcaf1ed4a4e0f121eda174
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- inclu

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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correct some missing-prototype warnings

This avoids the following warnings:
no previous prototype for 'bl2_arch_setup' [-Wmissing-prototypes]
no previous prototype for 'plat_log_get_prefix' [-Wmissi

correct some missing-prototype warnings

This avoids the following warnings:
no previous prototype for 'bl2_arch_setup' [-Wmissing-prototypes]
no previous prototype for 'plat_log_get_prefix' [-Wmissing-prototypes]

Also correct a compilation issue if BL2_IN_XIP_MEM is enabled:
uintptr_t is not defined.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this proje

Standardise header guards across codebase

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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