1# 2# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Use the GICv3 driver on the FVP by default 8FVP_USE_GIC_DRIVER := FVP_GICV3 9 10# Use the SP804 timer instead of the generic one 11FVP_USE_SP804_TIMER := 0 12 13# Default cluster count for FVP 14FVP_CLUSTER_COUNT := 2 15 16# Default number of CPUs per cluster on FVP 17FVP_MAX_CPUS_PER_CLUSTER := 4 18 19# Default number of threads per CPU on FVP 20FVP_MAX_PE_PER_CPU := 1 21 22FVP_DT_PREFIX := fvp-base-gicv3-psci 23 24$(eval $(call assert_boolean,FVP_USE_SP804_TIMER)) 25$(eval $(call add_define,FVP_USE_SP804_TIMER)) 26 27# The FVP platform depends on this macro to build with correct GIC driver. 28$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 29 30# Pass FVP_CLUSTER_COUNT to the build system. 31$(eval $(call add_define,FVP_CLUSTER_COUNT)) 32 33# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 34$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 35 36# Pass FVP_MAX_PE_PER_CPU to the build system. 37$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 38 39# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 40# choose the CCI driver , else the CCN driver 41ifeq ($(FVP_CLUSTER_COUNT), 0) 42$(error "Incorrect cluster count specified for FVP port") 43else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 44FVP_INTERCONNECT_DRIVER := FVP_CCI 45else 46FVP_INTERCONNECT_DRIVER := FVP_CCN 47endif 48 49$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 50 51FVP_GICV3_SOURCES := drivers/arm/gic/common/gic_common.c \ 52 drivers/arm/gic/v3/gicv3_main.c \ 53 drivers/arm/gic/v3/gicv3_helpers.c \ 54 plat/common/plat_gicv3.c \ 55 plat/arm/common/arm_gicv3.c 56 57# Choose the GIC sources depending upon the how the FVP will be invoked 58ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 59FVP_GIC_SOURCES := ${FVP_GICV3_SOURCES} \ 60 drivers/arm/gic/v3/gic500.c 61else ifeq (${FVP_USE_GIC_DRIVER},FVP_GIC600) 62FVP_GIC_SOURCES := ${FVP_GICV3_SOURCES} \ 63 drivers/arm/gic/v3/gic600.c 64else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 65FVP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ 66 drivers/arm/gic/v2/gicv2_main.c \ 67 drivers/arm/gic/v2/gicv2_helpers.c \ 68 plat/common/plat_gicv2.c \ 69 plat/arm/common/arm_gicv2.c 70 71FVP_DT_PREFIX := fvp-base-gicv2-psci 72else 73$(error "Incorrect GIC driver chosen on FVP port") 74endif 75 76ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 77FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 78else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 79FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 80 plat/arm/common/arm_ccn.c 81else 82$(error "Incorrect CCN driver chosen on FVP port") 83endif 84 85FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 86 plat/arm/board/fvp/fvp_security.c \ 87 plat/arm/common/arm_tzc400.c 88 89 90PLAT_INCLUDES := -Iplat/arm/board/fvp/include 91 92 93PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 94 95FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 96 97ifeq (${ARCH}, aarch64) 98 99# select a different set of CPU files, depending on whether we compile with 100# hardware assisted coherency configurations or not 101ifeq (${HW_ASSISTED_COHERENCY}, 0) 102 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 103 lib/cpus/aarch64/cortex_a53.S \ 104 lib/cpus/aarch64/cortex_a57.S \ 105 lib/cpus/aarch64/cortex_a72.S \ 106 lib/cpus/aarch64/cortex_a73.S 107else 108 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 109 lib/cpus/aarch64/cortex_a75.S \ 110 lib/cpus/aarch64/cortex_a76.S \ 111 lib/cpus/aarch64/cortex_a76ae.S \ 112 lib/cpus/aarch64/neoverse_n1.S \ 113 lib/cpus/aarch64/neoverse_e1.S \ 114 lib/cpus/aarch64/cortex_deimos.S \ 115 lib/cpus/aarch64/neoverse_zeus.S 116endif 117 118else 119FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S 120endif 121 122BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 123 drivers/arm/sp805/sp805.c \ 124 drivers/io/io_semihosting.c \ 125 lib/semihosting/semihosting.c \ 126 lib/semihosting/${ARCH}/semihosting_call.S \ 127 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 128 plat/arm/board/fvp/fvp_bl1_setup.c \ 129 plat/arm/board/fvp/fvp_io_storage.c \ 130 plat/arm/board/fvp/fvp_trusted_boot.c \ 131 ${FVP_CPU_LIBS} \ 132 ${FVP_INTERCONNECT_SOURCES} 133 134 135BL2_SOURCES += drivers/io/io_semihosting.c \ 136 lib/utils/mem_region.c \ 137 lib/semihosting/semihosting.c \ 138 lib/semihosting/${ARCH}/semihosting_call.S \ 139 plat/arm/board/fvp/fvp_bl2_setup.c \ 140 plat/arm/board/fvp/fvp_io_storage.c \ 141 plat/arm/board/fvp/fvp_trusted_boot.c \ 142 plat/arm/common/arm_nor_psci_mem_protect.c \ 143 ${FVP_SECURITY_SOURCES} 144 145 146 147ifeq (${BL2_AT_EL3},1) 148BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 149 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 150 ${FVP_CPU_LIBS} \ 151 ${FVP_INTERCONNECT_SOURCES} 152endif 153 154ifeq (${FVP_USE_SP804_TIMER},1) 155BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 156endif 157 158BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 159 ${FVP_SECURITY_SOURCES} 160 161BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 162 drivers/arm/smmu/smmu_v3.c \ 163 drivers/cfi/v2m/v2m_flash.c \ 164 lib/utils/mem_region.c \ 165 plat/arm/board/fvp/fvp_bl31_setup.c \ 166 plat/arm/board/fvp/fvp_pm.c \ 167 plat/arm/board/fvp/fvp_topology.c \ 168 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 169 plat/arm/common/arm_nor_psci_mem_protect.c \ 170 ${FVP_CPU_LIBS} \ 171 ${FVP_GIC_SOURCES} \ 172 ${FVP_INTERCONNECT_SOURCES} \ 173 ${FVP_SECURITY_SOURCES} 174 175# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 176ifdef UNIX_MK 177FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 178FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 179 ${PLAT}_tb_fw_config.dts \ 180 ${PLAT}_soc_fw_config.dts \ 181 ${PLAT}_nt_fw_config.dts \ 182 ) 183 184FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 185FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 186FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 187 188ifeq (${SPD},tspd) 189FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 190FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 191 192# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 193$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config)) 194endif 195 196# Add the TB_FW_CONFIG to FIP and specify the same to certtool 197$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config)) 198# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 199$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config)) 200# Add the NT_FW_CONFIG to FIP and specify the same to certtool 201$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config)) 202 203FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 204$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 205 206# Add the HW_CONFIG to FIP and specify the same to certtool 207$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config)) 208endif 209 210# Enable Activity Monitor Unit extensions by default 211ENABLE_AMU := 1 212 213# Enable dynamic mitigation support by default 214DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 215 216ifneq (${RESET_TO_BL31},1) 217# Enable reclaiming of BL31 initialisation code for secondary cores stacks for 218# FVP. We cannot enable PIE for this case because the overlayed init section 219# creates some dynamic relocations which cannot be handled by the fixup 220# logic currently. 221RECLAIM_INIT_CODE := 1 222else 223# Enable PIE support when RESET_TO_BL31=1 224ENABLE_PIE := 1 225endif 226 227ifeq (${ENABLE_AMU},1) 228BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 229 lib/cpus/aarch64/cpuamu_helpers.S 230 231ifeq (${HW_ASSISTED_COHERENCY}, 1) 232BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 233 lib/cpus/aarch64/neoverse_n1_pubsub.c 234endif 235endif 236 237ifeq (${RAS_EXTENSION},1) 238BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 239endif 240 241ifneq (${ENABLE_STACK_PROTECTOR},0) 242PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 243endif 244 245ifeq (${ARCH},aarch32) 246 NEED_BL32 := yes 247endif 248 249# Enable the dynamic translation tables library. 250ifeq (${ARCH},aarch32) 251 ifeq (${RESET_TO_SP_MIN},1) 252 BL32_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 253 endif 254else # if AArch64 255 ifeq (${RESET_TO_BL31},1) 256 BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 257 endif 258 ifeq (${ENABLE_SPM},1) 259 ifeq (${SPM_MM},0) 260 BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 261 endif 262 endif 263 ifeq (${SPD},trusty) 264 BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 265 endif 266endif 267 268# Add support for platform supplied linker script for BL31 build 269$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 270 271ifneq (${BL2_AT_EL3}, 0) 272 override BL1_SOURCES = 273endif 274 275include plat/arm/board/common/board_common.mk 276include plat/arm/common/arm_common.mk 277 278# FVP being a development platform, enable capability to disable Authentication 279# dynamically if TRUSTED_BOARD_BOOT is set. 280ifeq (${TRUSTED_BOARD_BOOT}, 1) 281 DYN_DISABLE_AUTH := 1 282endif 283