1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gicv3.h> 12 #include <interrupt_props.h> 13 #include <spinlock.h> 14 #include "gicv3_private.h" 15 16 const gicv3_driver_data_t *gicv3_driver_data; 17 static unsigned int gicv2_compat; 18 19 /* 20 * Spinlock to guard registers needing read-modify-write. APIs protected by this 21 * spinlock are used either at boot time (when only a single CPU is active), or 22 * when the system is fully coherent. 23 */ 24 static spinlock_t gic_lock; 25 26 /* 27 * Redistributor power operations are weakly bound so that they can be 28 * overridden 29 */ 30 #pragma weak gicv3_rdistif_off 31 #pragma weak gicv3_rdistif_on 32 33 34 /* Helper macros to save and restore GICD registers to and from the context */ 35 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 36 do { \ 37 for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \ 38 int_id += (1 << REG##_SHIFT)) { \ 39 gicd_write_##reg(base, int_id, \ 40 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT]); \ 41 } \ 42 } while (0) 43 44 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 45 do { \ 46 for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \ 47 int_id += (1 << REG##_SHIFT)) { \ 48 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT] =\ 49 gicd_read_##reg(base, int_id); \ 50 } \ 51 } while (0) 52 53 54 /******************************************************************************* 55 * This function initialises the ARM GICv3 driver in EL3 with provided platform 56 * inputs. 57 ******************************************************************************/ 58 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 59 { 60 unsigned int gic_version; 61 62 assert(plat_driver_data); 63 assert(plat_driver_data->gicd_base); 64 assert(plat_driver_data->gicr_base); 65 assert(plat_driver_data->rdistif_num); 66 assert(plat_driver_data->rdistif_base_addrs); 67 68 assert(IS_IN_EL3()); 69 70 #if !ERROR_DEPRECATED 71 if (plat_driver_data->interrupt_props == NULL) { 72 /* Interrupt properties array size must be 0 */ 73 assert(plat_driver_data->interrupt_props_num == 0); 74 75 /* 76 * The platform should provide a list of at least one type of 77 * interrupt. 78 */ 79 assert(plat_driver_data->g0_interrupt_array || 80 plat_driver_data->g1s_interrupt_array); 81 82 /* 83 * If there are no interrupts of a particular type, then the 84 * number of interrupts of that type should be 0 and vice-versa. 85 */ 86 assert(plat_driver_data->g0_interrupt_array ? 87 plat_driver_data->g0_interrupt_num : 88 plat_driver_data->g0_interrupt_num == 0); 89 assert(plat_driver_data->g1s_interrupt_array ? 90 plat_driver_data->g1s_interrupt_num : 91 plat_driver_data->g1s_interrupt_num == 0); 92 } 93 #else 94 assert(plat_driver_data->interrupt_props != NULL); 95 assert(plat_driver_data->interrupt_props_num > 0); 96 #endif 97 98 /* Check for system register support */ 99 #ifdef AARCH32 100 assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)); 101 #else 102 assert(read_id_aa64pfr0_el1() & 103 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)); 104 #endif /* AARCH32 */ 105 106 /* The GIC version should be 3.0 */ 107 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 108 gic_version >>= PIDR2_ARCH_REV_SHIFT; 109 gic_version &= PIDR2_ARCH_REV_MASK; 110 assert(gic_version == ARCH_REV_GICV3); 111 112 /* 113 * Find out whether the GIC supports the GICv2 compatibility mode. The 114 * ARE_S bit resets to 0 if supported 115 */ 116 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 117 gicv2_compat >>= CTLR_ARE_S_SHIFT; 118 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); 119 120 /* 121 * Find the base address of each implemented Redistributor interface. 122 * The number of interfaces should be equal to the number of CPUs in the 123 * system. The memory for saving these addresses has to be allocated by 124 * the platform port 125 */ 126 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 127 plat_driver_data->rdistif_num, 128 plat_driver_data->gicr_base, 129 plat_driver_data->mpidr_to_core_pos); 130 131 gicv3_driver_data = plat_driver_data; 132 133 /* 134 * The GIC driver data is initialized by the primary CPU with caches 135 * enabled. When the secondary CPU boots up, it initializes the 136 * GICC/GICR interface with the caches disabled. Hence flush the 137 * driver data to ensure coherency. This is not required if the 138 * platform has HW_ASSISTED_COHERENCY enabled. 139 */ 140 #if !HW_ASSISTED_COHERENCY 141 flush_dcache_range((uintptr_t) &gicv3_driver_data, 142 sizeof(gicv3_driver_data)); 143 flush_dcache_range((uintptr_t) gicv3_driver_data, 144 sizeof(*gicv3_driver_data)); 145 #endif 146 147 INFO("GICv3 %s legacy support detected." 148 " ARM GICV3 driver initialized in EL3\n", 149 gicv2_compat ? "with" : "without"); 150 } 151 152 /******************************************************************************* 153 * This function initialises the GIC distributor interface based upon the data 154 * provided by the platform while initialising the driver. 155 ******************************************************************************/ 156 void gicv3_distif_init(void) 157 { 158 unsigned int bitmap = 0; 159 160 assert(gicv3_driver_data); 161 assert(gicv3_driver_data->gicd_base); 162 163 assert(IS_IN_EL3()); 164 165 /* 166 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 167 * the ARE_S bit. The Distributor might generate a system error 168 * otherwise. 169 */ 170 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 171 CTLR_ENABLE_G0_BIT | 172 CTLR_ENABLE_G1S_BIT | 173 CTLR_ENABLE_G1NS_BIT, 174 RWP_TRUE); 175 176 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 177 gicd_set_ctlr(gicv3_driver_data->gicd_base, 178 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 179 180 /* Set the default attribute of all SPIs */ 181 gicv3_spis_configure_defaults(gicv3_driver_data->gicd_base); 182 183 #if !ERROR_DEPRECATED 184 if (gicv3_driver_data->interrupt_props != NULL) { 185 #endif 186 bitmap = gicv3_secure_spis_configure_props( 187 gicv3_driver_data->gicd_base, 188 gicv3_driver_data->interrupt_props, 189 gicv3_driver_data->interrupt_props_num); 190 #if !ERROR_DEPRECATED 191 } else { 192 assert(gicv3_driver_data->g1s_interrupt_array || 193 gicv3_driver_data->g0_interrupt_array); 194 195 /* Configure the G1S SPIs */ 196 if (gicv3_driver_data->g1s_interrupt_array) { 197 gicv3_secure_spis_configure(gicv3_driver_data->gicd_base, 198 gicv3_driver_data->g1s_interrupt_num, 199 gicv3_driver_data->g1s_interrupt_array, 200 INTR_GROUP1S); 201 bitmap |= CTLR_ENABLE_G1S_BIT; 202 } 203 204 /* Configure the G0 SPIs */ 205 if (gicv3_driver_data->g0_interrupt_array) { 206 gicv3_secure_spis_configure(gicv3_driver_data->gicd_base, 207 gicv3_driver_data->g0_interrupt_num, 208 gicv3_driver_data->g0_interrupt_array, 209 INTR_GROUP0); 210 bitmap |= CTLR_ENABLE_G0_BIT; 211 } 212 } 213 #endif 214 215 /* Enable the secure SPIs now that they have been configured */ 216 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 217 } 218 219 /******************************************************************************* 220 * This function initialises the GIC Redistributor interface of the calling CPU 221 * (identified by the 'proc_num' parameter) based upon the data provided by the 222 * platform while initialising the driver. 223 ******************************************************************************/ 224 void gicv3_rdistif_init(unsigned int proc_num) 225 { 226 uintptr_t gicr_base; 227 unsigned int bitmap = 0; 228 uint32_t ctlr; 229 230 assert(gicv3_driver_data); 231 assert(proc_num < gicv3_driver_data->rdistif_num); 232 assert(gicv3_driver_data->rdistif_base_addrs); 233 assert(gicv3_driver_data->gicd_base); 234 235 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base); 236 assert(ctlr & CTLR_ARE_S_BIT); 237 238 assert(IS_IN_EL3()); 239 240 /* Power on redistributor */ 241 gicv3_rdistif_on(proc_num); 242 243 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 244 245 /* Set the default attribute of all SGIs and PPIs */ 246 gicv3_ppi_sgi_configure_defaults(gicr_base); 247 248 #if !ERROR_DEPRECATED 249 if (gicv3_driver_data->interrupt_props != NULL) { 250 #endif 251 bitmap = gicv3_secure_ppi_sgi_configure_props(gicr_base, 252 gicv3_driver_data->interrupt_props, 253 gicv3_driver_data->interrupt_props_num); 254 #if !ERROR_DEPRECATED 255 } else { 256 assert(gicv3_driver_data->g1s_interrupt_array || 257 gicv3_driver_data->g0_interrupt_array); 258 259 /* Configure the G1S SGIs/PPIs */ 260 if (gicv3_driver_data->g1s_interrupt_array) { 261 gicv3_secure_ppi_sgi_configure(gicr_base, 262 gicv3_driver_data->g1s_interrupt_num, 263 gicv3_driver_data->g1s_interrupt_array, 264 INTR_GROUP1S); 265 bitmap |= CTLR_ENABLE_G1S_BIT; 266 } 267 268 /* Configure the G0 SGIs/PPIs */ 269 if (gicv3_driver_data->g0_interrupt_array) { 270 gicv3_secure_ppi_sgi_configure(gicr_base, 271 gicv3_driver_data->g0_interrupt_num, 272 gicv3_driver_data->g0_interrupt_array, 273 INTR_GROUP0); 274 bitmap |= CTLR_ENABLE_G0_BIT; 275 } 276 } 277 #endif 278 279 /* Enable interrupt groups as required, if not already */ 280 if ((ctlr & bitmap) != bitmap) 281 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 282 } 283 284 /******************************************************************************* 285 * Functions to perform power operations on GIC Redistributor 286 ******************************************************************************/ 287 void gicv3_rdistif_off(unsigned int proc_num) 288 { 289 return; 290 } 291 292 void gicv3_rdistif_on(unsigned int proc_num) 293 { 294 return; 295 } 296 297 /******************************************************************************* 298 * This function enables the GIC CPU interface of the calling CPU using only 299 * system register accesses. 300 ******************************************************************************/ 301 void gicv3_cpuif_enable(unsigned int proc_num) 302 { 303 uintptr_t gicr_base; 304 unsigned int scr_el3; 305 unsigned int icc_sre_el3; 306 307 assert(gicv3_driver_data); 308 assert(proc_num < gicv3_driver_data->rdistif_num); 309 assert(gicv3_driver_data->rdistif_base_addrs); 310 assert(IS_IN_EL3()); 311 312 /* Mark the connected core as awake */ 313 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 314 gicv3_rdistif_mark_core_awake(gicr_base); 315 316 /* Disable the legacy interrupt bypass */ 317 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 318 319 /* 320 * Enable system register access for EL3 and allow lower exception 321 * levels to configure the same for themselves. If the legacy mode is 322 * not supported, the SRE bit is RAO/WI 323 */ 324 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 325 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 326 327 scr_el3 = read_scr_el3(); 328 329 /* 330 * Switch to NS state to write Non secure ICC_SRE_EL1 and 331 * ICC_SRE_EL2 registers. 332 */ 333 write_scr_el3(scr_el3 | SCR_NS_BIT); 334 isb(); 335 336 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 337 write_icc_sre_el1(ICC_SRE_SRE_BIT); 338 isb(); 339 340 /* Switch to secure state. */ 341 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 342 isb(); 343 344 /* Program the idle priority in the PMR */ 345 write_icc_pmr_el1(GIC_PRI_MASK); 346 347 /* Enable Group0 interrupts */ 348 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 349 350 /* Enable Group1 Secure interrupts */ 351 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 352 IGRPEN1_EL3_ENABLE_G1S_BIT); 353 354 /* Write the secure ICC_SRE_EL1 register */ 355 write_icc_sre_el1(ICC_SRE_SRE_BIT); 356 isb(); 357 } 358 359 /******************************************************************************* 360 * This function disables the GIC CPU interface of the calling CPU using 361 * only system register accesses. 362 ******************************************************************************/ 363 void gicv3_cpuif_disable(unsigned int proc_num) 364 { 365 uintptr_t gicr_base; 366 367 assert(gicv3_driver_data); 368 assert(proc_num < gicv3_driver_data->rdistif_num); 369 assert(gicv3_driver_data->rdistif_base_addrs); 370 371 assert(IS_IN_EL3()); 372 373 /* Disable legacy interrupt bypass */ 374 write_icc_sre_el3(read_icc_sre_el3() | 375 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 376 377 /* Disable Group0 interrupts */ 378 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 379 ~IGRPEN1_EL1_ENABLE_G0_BIT); 380 381 /* Disable Group1 Secure and Non-Secure interrupts */ 382 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 383 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 384 IGRPEN1_EL3_ENABLE_G1S_BIT)); 385 386 /* Synchronise accesses to group enable registers */ 387 isb(); 388 389 /* Mark the connected core as asleep */ 390 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 391 gicv3_rdistif_mark_core_asleep(gicr_base); 392 } 393 394 /******************************************************************************* 395 * This function returns the id of the highest priority pending interrupt at 396 * the GIC cpu interface. 397 ******************************************************************************/ 398 unsigned int gicv3_get_pending_interrupt_id(void) 399 { 400 unsigned int id; 401 402 assert(IS_IN_EL3()); 403 id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 404 405 /* 406 * If the ID is special identifier corresponding to G1S or G1NS 407 * interrupt, then read the highest pending group 1 interrupt. 408 */ 409 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) 410 return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 411 412 return id; 413 } 414 415 /******************************************************************************* 416 * This function returns the type of the highest priority pending interrupt at 417 * the GIC cpu interface. The return values can be one of the following : 418 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 419 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 420 * 0 - 1019 : The interrupt type is secure Group 0. 421 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 422 * sufficient priority to be signaled 423 ******************************************************************************/ 424 unsigned int gicv3_get_pending_interrupt_type(void) 425 { 426 assert(IS_IN_EL3()); 427 return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 428 } 429 430 /******************************************************************************* 431 * This function returns the type of the interrupt id depending upon the group 432 * this interrupt has been configured under by the interrupt controller i.e. 433 * group0 or group1 Secure / Non Secure. The return value can be one of the 434 * following : 435 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 436 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 437 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 438 * interrupt. 439 ******************************************************************************/ 440 unsigned int gicv3_get_interrupt_type(unsigned int id, 441 unsigned int proc_num) 442 { 443 unsigned int igroup, grpmodr; 444 uintptr_t gicr_base; 445 446 assert(IS_IN_EL3()); 447 assert(gicv3_driver_data); 448 449 /* Ensure the parameters are valid */ 450 assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID); 451 assert(proc_num < gicv3_driver_data->rdistif_num); 452 453 /* All LPI interrupts are Group 1 non secure */ 454 if (id >= MIN_LPI_ID) 455 return INTR_GROUP1NS; 456 457 if (id < MIN_SPI_ID) { 458 assert(gicv3_driver_data->rdistif_base_addrs); 459 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 460 igroup = gicr_get_igroupr0(gicr_base, id); 461 grpmodr = gicr_get_igrpmodr0(gicr_base, id); 462 } else { 463 assert(gicv3_driver_data->gicd_base); 464 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id); 465 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id); 466 } 467 468 /* 469 * If the IGROUP bit is set, then it is a Group 1 Non secure 470 * interrupt 471 */ 472 if (igroup) 473 return INTR_GROUP1NS; 474 475 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 476 if (grpmodr) 477 return INTR_GROUP1S; 478 479 /* Else it is a Group 0 Secure interrupt */ 480 return INTR_GROUP0; 481 } 482 483 /***************************************************************************** 484 * Function to save and disable the GIC ITS register context. The power 485 * management of GIC ITS is implementation-defined and this function doesn't 486 * save any memory structures required to support ITS. As the sequence to save 487 * this state is implementation defined, it should be executed in platform 488 * specific code. Calling this function alone and then powering down the GIC and 489 * ITS without implementing the aforementioned platform specific code will 490 * corrupt the ITS state. 491 * 492 * This function must be invoked after the GIC CPU interface is disabled. 493 *****************************************************************************/ 494 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx) 495 { 496 int i; 497 498 assert(gicv3_driver_data); 499 assert(IS_IN_EL3()); 500 assert(its_ctx); 501 assert(gits_base); 502 503 its_ctx->gits_ctlr = gits_read_ctlr(gits_base); 504 505 /* Disable the ITS */ 506 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & 507 (~GITS_CTLR_ENABLED_BIT)); 508 509 /* Wait for quiescent state */ 510 gits_wait_for_quiescent_bit(gits_base); 511 512 its_ctx->gits_cbaser = gits_read_cbaser(gits_base); 513 its_ctx->gits_cwriter = gits_read_cwriter(gits_base); 514 515 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++) 516 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); 517 } 518 519 /***************************************************************************** 520 * Function to restore the GIC ITS register context. The power 521 * management of GIC ITS is implementation defined and this function doesn't 522 * restore any memory structures required to support ITS. The assumption is 523 * that these structures are in memory and are retained during system suspend. 524 * 525 * This must be invoked before the GIC CPU interface is enabled. 526 *****************************************************************************/ 527 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx) 528 { 529 int i; 530 531 assert(gicv3_driver_data); 532 assert(IS_IN_EL3()); 533 assert(its_ctx); 534 assert(gits_base); 535 536 /* Assert that the GITS is disabled and quiescent */ 537 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0); 538 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0); 539 540 gits_write_cbaser(gits_base, its_ctx->gits_cbaser); 541 gits_write_cwriter(gits_base, its_ctx->gits_cwriter); 542 543 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++) 544 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); 545 546 /* Restore the ITS CTLR but leave the ITS disabled */ 547 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & 548 (~GITS_CTLR_ENABLED_BIT)); 549 } 550 551 /***************************************************************************** 552 * Function to save the GIC Redistributor register context. This function 553 * must be invoked after CPU interface disable and prior to Distributor save. 554 *****************************************************************************/ 555 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx) 556 { 557 uintptr_t gicr_base; 558 unsigned int int_id; 559 560 assert(gicv3_driver_data); 561 assert(proc_num < gicv3_driver_data->rdistif_num); 562 assert(gicv3_driver_data->rdistif_base_addrs); 563 assert(IS_IN_EL3()); 564 assert(rdist_ctx); 565 566 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 567 568 /* 569 * Wait for any write to GICR_CTLR to complete before trying to save any 570 * state. 571 */ 572 gicr_wait_for_pending_write(gicr_base); 573 574 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 575 576 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 577 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 578 579 rdist_ctx->gicr_igroupr0 = gicr_read_igroupr0(gicr_base); 580 rdist_ctx->gicr_isenabler0 = gicr_read_isenabler0(gicr_base); 581 rdist_ctx->gicr_ispendr0 = gicr_read_ispendr0(gicr_base); 582 rdist_ctx->gicr_isactiver0 = gicr_read_isactiver0(gicr_base); 583 rdist_ctx->gicr_icfgr0 = gicr_read_icfgr0(gicr_base); 584 rdist_ctx->gicr_icfgr1 = gicr_read_icfgr1(gicr_base); 585 rdist_ctx->gicr_igrpmodr0 = gicr_read_igrpmodr0(gicr_base); 586 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 587 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM; 588 int_id += (1 << IPRIORITYR_SHIFT)) { 589 rdist_ctx->gicr_ipriorityr[(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT] = 590 gicr_read_ipriorityr(gicr_base, int_id); 591 } 592 593 594 /* 595 * Call the pre-save hook that implements the IMP DEF sequence that may 596 * be required on some GIC implementations. As this may need to access 597 * the Redistributor registers, we pass it proc_num. 598 */ 599 gicv3_distif_pre_save(proc_num); 600 } 601 602 /***************************************************************************** 603 * Function to restore the GIC Redistributor register context. We disable 604 * LPI and per-cpu interrupts before we start restore of the Redistributor. 605 * This function must be invoked after Distributor restore but prior to 606 * CPU interface enable. The pending and active interrupts are restored 607 * after the interrupts are fully configured and enabled. 608 *****************************************************************************/ 609 void gicv3_rdistif_init_restore(unsigned int proc_num, 610 const gicv3_redist_ctx_t * const rdist_ctx) 611 { 612 uintptr_t gicr_base; 613 unsigned int int_id; 614 615 assert(gicv3_driver_data); 616 assert(proc_num < gicv3_driver_data->rdistif_num); 617 assert(gicv3_driver_data->rdistif_base_addrs); 618 assert(IS_IN_EL3()); 619 assert(rdist_ctx); 620 621 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 622 623 /* Power on redistributor */ 624 gicv3_rdistif_on(proc_num); 625 626 /* 627 * Call the post-restore hook that implements the IMP DEF sequence that 628 * may be required on some GIC implementations. As this may need to 629 * access the Redistributor registers, we pass it proc_num. 630 */ 631 gicv3_distif_post_restore(proc_num); 632 633 /* 634 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a 635 * more scalable approach as it avoids clearing the enable bits in the 636 * GICD_CTLR 637 */ 638 gicr_write_icenabler0(gicr_base, ~0); 639 /* Wait for pending writes to GICR_ICENABLER */ 640 gicr_wait_for_pending_write(gicr_base); 641 642 /* 643 * Disable the LPIs to avoid unpredictable behavior when writing to 644 * GICR_PROPBASER and GICR_PENDBASER. 645 */ 646 gicr_write_ctlr(gicr_base, 647 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 648 649 /* Restore registers' content */ 650 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 651 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 652 653 gicr_write_igroupr0(gicr_base, rdist_ctx->gicr_igroupr0); 654 655 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM; 656 int_id += (1 << IPRIORITYR_SHIFT)) { 657 gicr_write_ipriorityr(gicr_base, int_id, 658 rdist_ctx->gicr_ipriorityr[ 659 (int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT]); 660 } 661 662 gicr_write_icfgr0(gicr_base, rdist_ctx->gicr_icfgr0); 663 gicr_write_icfgr1(gicr_base, rdist_ctx->gicr_icfgr1); 664 gicr_write_igrpmodr0(gicr_base, rdist_ctx->gicr_igrpmodr0); 665 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 666 667 /* Restore after group and priorities are set */ 668 gicr_write_ispendr0(gicr_base, rdist_ctx->gicr_ispendr0); 669 gicr_write_isactiver0(gicr_base, rdist_ctx->gicr_isactiver0); 670 671 /* 672 * Wait for all writes to the Distributor to complete before enabling 673 * the SGI and PPIs. 674 */ 675 gicr_wait_for_upstream_pending_write(gicr_base); 676 gicr_write_isenabler0(gicr_base, rdist_ctx->gicr_isenabler0); 677 678 /* 679 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 680 * the first write to GICR_CTLR was still in flight (this write only 681 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 682 * bit). 683 */ 684 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 685 gicr_wait_for_pending_write(gicr_base); 686 } 687 688 /***************************************************************************** 689 * Function to save the GIC Distributor register context. This function 690 * must be invoked after CPU interface disable and Redistributor save. 691 *****************************************************************************/ 692 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 693 { 694 unsigned int num_ints; 695 696 assert(gicv3_driver_data); 697 assert(gicv3_driver_data->gicd_base); 698 assert(IS_IN_EL3()); 699 assert(dist_ctx); 700 701 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 702 703 num_ints = gicd_read_typer(gicd_base); 704 num_ints &= TYPER_IT_LINES_NO_MASK; 705 num_ints = (num_ints + 1) << 5; 706 707 assert(num_ints <= MAX_SPI_ID + 1); 708 709 /* Wait for pending write to complete */ 710 gicd_wait_for_pending_write(gicd_base); 711 712 /* Save the GICD_CTLR */ 713 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 714 715 /* Save GICD_IGROUPR for INTIDs 32 - 1020 */ 716 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); 717 718 /* Save GICD_ISENABLER for INT_IDs 32 - 1020 */ 719 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); 720 721 /* Save GICD_ISPENDR for INTIDs 32 - 1020 */ 722 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); 723 724 /* Save GICD_ISACTIVER for INTIDs 32 - 1020 */ 725 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); 726 727 /* Save GICD_IPRIORITYR for INTIDs 32 - 1020 */ 728 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); 729 730 /* Save GICD_ICFGR for INTIDs 32 - 1020 */ 731 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); 732 733 /* Save GICD_IGRPMODR for INTIDs 32 - 1020 */ 734 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); 735 736 /* Save GICD_NSACR for INTIDs 32 - 1020 */ 737 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); 738 739 /* Save GICD_IROUTER for INTIDs 32 - 1024 */ 740 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); 741 742 /* 743 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 744 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 745 * driver. 746 */ 747 } 748 749 /***************************************************************************** 750 * Function to restore the GIC Distributor register context. We disable G0, G1S 751 * and G1NS interrupt groups before we start restore of the Distributor. This 752 * function must be invoked prior to Redistributor restore and CPU interface 753 * enable. The pending and active interrupts are restored after the interrupts 754 * are fully configured and enabled. 755 *****************************************************************************/ 756 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 757 { 758 unsigned int num_ints = 0; 759 760 assert(gicv3_driver_data); 761 assert(gicv3_driver_data->gicd_base); 762 assert(IS_IN_EL3()); 763 assert(dist_ctx); 764 765 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 766 767 /* 768 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 769 * the ARE_S bit. The Distributor might generate a system error 770 * otherwise. 771 */ 772 gicd_clr_ctlr(gicd_base, 773 CTLR_ENABLE_G0_BIT | 774 CTLR_ENABLE_G1S_BIT | 775 CTLR_ENABLE_G1NS_BIT, 776 RWP_TRUE); 777 778 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 779 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 780 781 num_ints = gicd_read_typer(gicd_base); 782 num_ints &= TYPER_IT_LINES_NO_MASK; 783 num_ints = (num_ints + 1) << 5; 784 785 assert(num_ints <= MAX_SPI_ID + 1); 786 787 /* Restore GICD_IGROUPR for INTIDs 32 - 1020 */ 788 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); 789 790 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1020 */ 791 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); 792 793 /* Restore GICD_ICFGR for INTIDs 32 - 1020 */ 794 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); 795 796 /* Restore GICD_IGRPMODR for INTIDs 32 - 1020 */ 797 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); 798 799 /* Restore GICD_NSACR for INTIDs 32 - 1020 */ 800 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); 801 802 /* Restore GICD_IROUTER for INTIDs 32 - 1020 */ 803 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); 804 805 /* 806 * Restore ISENABLER, ISPENDR and ISACTIVER after the interrupts are 807 * configured. 808 */ 809 810 /* Restore GICD_ISENABLER for INT_IDs 32 - 1020 */ 811 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); 812 813 /* Restore GICD_ISPENDR for INTIDs 32 - 1020 */ 814 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); 815 816 /* Restore GICD_ISACTIVER for INTIDs 32 - 1020 */ 817 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); 818 819 /* Restore the GICD_CTLR */ 820 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 821 gicd_wait_for_pending_write(gicd_base); 822 823 } 824 825 /******************************************************************************* 826 * This function gets the priority of the interrupt the processor is currently 827 * servicing. 828 ******************************************************************************/ 829 unsigned int gicv3_get_running_priority(void) 830 { 831 return read_icc_rpr_el1(); 832 } 833 834 /******************************************************************************* 835 * This function checks if the interrupt identified by id is active (whether the 836 * state is either active, or active and pending). The proc_num is used if the 837 * interrupt is SGI or PPI and programs the corresponding Redistributor 838 * interface. 839 ******************************************************************************/ 840 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num) 841 { 842 unsigned int value; 843 844 assert(gicv3_driver_data); 845 assert(gicv3_driver_data->gicd_base); 846 assert(proc_num < gicv3_driver_data->rdistif_num); 847 assert(gicv3_driver_data->rdistif_base_addrs); 848 assert(id <= MAX_SPI_ID); 849 850 if (id < MIN_SPI_ID) { 851 /* For SGIs and PPIs */ 852 value = gicr_get_isactiver0( 853 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 854 } else { 855 value = gicd_get_isactiver(gicv3_driver_data->gicd_base, id); 856 } 857 858 return value; 859 } 860 861 /******************************************************************************* 862 * This function enables the interrupt identified by id. The proc_num 863 * is used if the interrupt is SGI or PPI, and programs the corresponding 864 * Redistributor interface. 865 ******************************************************************************/ 866 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num) 867 { 868 assert(gicv3_driver_data); 869 assert(gicv3_driver_data->gicd_base); 870 assert(proc_num < gicv3_driver_data->rdistif_num); 871 assert(gicv3_driver_data->rdistif_base_addrs); 872 assert(id <= MAX_SPI_ID); 873 874 /* 875 * Ensure that any shared variable updates depending on out of band 876 * interrupt trigger are observed before enabling interrupt. 877 */ 878 dsbishst(); 879 if (id < MIN_SPI_ID) { 880 /* For SGIs and PPIs */ 881 gicr_set_isenabler0( 882 gicv3_driver_data->rdistif_base_addrs[proc_num], 883 id); 884 } else { 885 gicd_set_isenabler(gicv3_driver_data->gicd_base, id); 886 } 887 } 888 889 /******************************************************************************* 890 * This function disables the interrupt identified by id. The proc_num 891 * is used if the interrupt is SGI or PPI, and programs the corresponding 892 * Redistributor interface. 893 ******************************************************************************/ 894 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num) 895 { 896 assert(gicv3_driver_data); 897 assert(gicv3_driver_data->gicd_base); 898 assert(proc_num < gicv3_driver_data->rdistif_num); 899 assert(gicv3_driver_data->rdistif_base_addrs); 900 assert(id <= MAX_SPI_ID); 901 902 /* 903 * Disable interrupt, and ensure that any shared variable updates 904 * depending on out of band interrupt trigger are observed afterwards. 905 */ 906 if (id < MIN_SPI_ID) { 907 /* For SGIs and PPIs */ 908 gicr_set_icenabler0( 909 gicv3_driver_data->rdistif_base_addrs[proc_num], 910 id); 911 912 /* Write to clear enable requires waiting for pending writes */ 913 gicr_wait_for_pending_write( 914 gicv3_driver_data->rdistif_base_addrs[proc_num]); 915 } else { 916 gicd_set_icenabler(gicv3_driver_data->gicd_base, id); 917 918 /* Write to clear enable requires waiting for pending writes */ 919 gicd_wait_for_pending_write(gicv3_driver_data->gicd_base); 920 } 921 922 dsbishst(); 923 } 924 925 /******************************************************************************* 926 * This function sets the interrupt priority as supplied for the given interrupt 927 * id. 928 ******************************************************************************/ 929 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 930 unsigned int priority) 931 { 932 uintptr_t gicr_base; 933 934 assert(gicv3_driver_data); 935 assert(gicv3_driver_data->gicd_base); 936 assert(proc_num < gicv3_driver_data->rdistif_num); 937 assert(gicv3_driver_data->rdistif_base_addrs); 938 assert(id <= MAX_SPI_ID); 939 940 if (id < MIN_SPI_ID) { 941 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 942 gicr_set_ipriorityr(gicr_base, id, priority); 943 } else { 944 gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority); 945 } 946 } 947 948 /******************************************************************************* 949 * This function assigns group for the interrupt identified by id. The proc_num 950 * is used if the interrupt is SGI or PPI, and programs the corresponding 951 * Redistributor interface. The group can be any of GICV3_INTR_GROUP* 952 ******************************************************************************/ 953 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 954 unsigned int type) 955 { 956 unsigned int igroup = 0, grpmod = 0; 957 uintptr_t gicr_base; 958 959 assert(gicv3_driver_data); 960 assert(gicv3_driver_data->gicd_base); 961 assert(proc_num < gicv3_driver_data->rdistif_num); 962 assert(gicv3_driver_data->rdistif_base_addrs); 963 964 switch (type) { 965 case INTR_GROUP1S: 966 igroup = 0; 967 grpmod = 1; 968 break; 969 case INTR_GROUP0: 970 igroup = 0; 971 grpmod = 0; 972 break; 973 case INTR_GROUP1NS: 974 igroup = 1; 975 grpmod = 0; 976 break; 977 default: 978 assert(0); 979 } 980 981 if (id < MIN_SPI_ID) { 982 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 983 if (igroup) 984 gicr_set_igroupr0(gicr_base, id); 985 else 986 gicr_clr_igroupr0(gicr_base, id); 987 988 if (grpmod) 989 gicr_set_igrpmodr0(gicr_base, id); 990 else 991 gicr_clr_igrpmodr0(gicr_base, id); 992 } else { 993 /* Serialize read-modify-write to Distributor registers */ 994 spin_lock(&gic_lock); 995 if (igroup) 996 gicd_set_igroupr(gicv3_driver_data->gicd_base, id); 997 else 998 gicd_clr_igroupr(gicv3_driver_data->gicd_base, id); 999 1000 if (grpmod) 1001 gicd_set_igrpmodr(gicv3_driver_data->gicd_base, id); 1002 else 1003 gicd_clr_igrpmodr(gicv3_driver_data->gicd_base, id); 1004 spin_unlock(&gic_lock); 1005 } 1006 } 1007 1008 /******************************************************************************* 1009 * This function raises the specified Secure Group 0 SGI. 1010 * 1011 * The target parameter must be a valid MPIDR in the system. 1012 ******************************************************************************/ 1013 void gicv3_raise_secure_g0_sgi(int sgi_num, u_register_t target) 1014 { 1015 unsigned int tgt, aff3, aff2, aff1, aff0; 1016 uint64_t sgi_val; 1017 1018 /* Verify interrupt number is in the SGI range */ 1019 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID)); 1020 1021 /* Extract affinity fields from target */ 1022 aff0 = MPIDR_AFFLVL0_VAL(target); 1023 aff1 = MPIDR_AFFLVL1_VAL(target); 1024 aff2 = MPIDR_AFFLVL2_VAL(target); 1025 aff3 = MPIDR_AFFLVL3_VAL(target); 1026 1027 /* 1028 * Make target list from affinity 0, and ensure GICv3 SGI can target 1029 * this PE. 1030 */ 1031 assert(aff0 < GICV3_MAX_SGI_TARGETS); 1032 tgt = BIT(aff0); 1033 1034 /* Raise SGI to PE specified by its affinity */ 1035 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF, 1036 tgt); 1037 1038 /* 1039 * Ensure that any shared variable updates depending on out of band 1040 * interrupt trigger are observed before raising SGI. 1041 */ 1042 dsbishst(); 1043 write_icc_sgi0r_el1(sgi_val); 1044 isb(); 1045 } 1046 1047 /******************************************************************************* 1048 * This function sets the interrupt routing for the given SPI interrupt id. 1049 * The interrupt routing is specified in routing mode and mpidr. 1050 * 1051 * The routing mode can be either of: 1052 * - GICV3_IRM_ANY 1053 * - GICV3_IRM_PE 1054 * 1055 * The mpidr is the affinity of the PE to which the interrupt will be routed, 1056 * and is ignored for routing mode GICV3_IRM_ANY. 1057 ******************************************************************************/ 1058 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr) 1059 { 1060 unsigned long long aff; 1061 uint64_t router; 1062 1063 assert(gicv3_driver_data); 1064 assert(gicv3_driver_data->gicd_base); 1065 1066 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE)); 1067 assert(id >= MIN_SPI_ID && id <= MAX_SPI_ID); 1068 1069 aff = gicd_irouter_val_from_mpidr(mpidr, irm); 1070 gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff); 1071 1072 /* 1073 * In implementations that do not require 1 of N distribution of SPIs, 1074 * IRM might be RAZ/WI. Read back and verify IRM bit. 1075 */ 1076 if (irm == GICV3_IRM_ANY) { 1077 router = gicd_read_irouter(gicv3_driver_data->gicd_base, id); 1078 if (!((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK)) { 1079 ERROR("GICv3 implementation doesn't support routing ANY\n"); 1080 panic(); 1081 } 1082 } 1083 } 1084 1085 /******************************************************************************* 1086 * This function clears the pending status of an interrupt identified by id. 1087 * The proc_num is used if the interrupt is SGI or PPI, and programs the 1088 * corresponding Redistributor interface. 1089 ******************************************************************************/ 1090 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num) 1091 { 1092 assert(gicv3_driver_data); 1093 assert(gicv3_driver_data->gicd_base); 1094 assert(proc_num < gicv3_driver_data->rdistif_num); 1095 assert(gicv3_driver_data->rdistif_base_addrs); 1096 1097 /* 1098 * Clear pending interrupt, and ensure that any shared variable updates 1099 * depending on out of band interrupt trigger are observed afterwards. 1100 */ 1101 if (id < MIN_SPI_ID) { 1102 /* For SGIs and PPIs */ 1103 gicr_set_icpendr0(gicv3_driver_data->rdistif_base_addrs[proc_num], 1104 id); 1105 } else { 1106 gicd_set_icpendr(gicv3_driver_data->gicd_base, id); 1107 } 1108 dsbishst(); 1109 } 1110 1111 /******************************************************************************* 1112 * This function sets the pending status of an interrupt identified by id. 1113 * The proc_num is used if the interrupt is SGI or PPI and programs the 1114 * corresponding Redistributor interface. 1115 ******************************************************************************/ 1116 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num) 1117 { 1118 assert(gicv3_driver_data); 1119 assert(gicv3_driver_data->gicd_base); 1120 assert(proc_num < gicv3_driver_data->rdistif_num); 1121 assert(gicv3_driver_data->rdistif_base_addrs); 1122 1123 /* 1124 * Ensure that any shared variable updates depending on out of band 1125 * interrupt trigger are observed before setting interrupt pending. 1126 */ 1127 dsbishst(); 1128 if (id < MIN_SPI_ID) { 1129 /* For SGIs and PPIs */ 1130 gicr_set_ispendr0(gicv3_driver_data->rdistif_base_addrs[proc_num], 1131 id); 1132 } else { 1133 gicd_set_ispendr(gicv3_driver_data->gicd_base, id); 1134 } 1135 } 1136 1137 /******************************************************************************* 1138 * This function sets the PMR register with the supplied value. Returns the 1139 * original PMR. 1140 ******************************************************************************/ 1141 unsigned int gicv3_set_pmr(unsigned int mask) 1142 { 1143 unsigned int old_mask; 1144 1145 old_mask = read_icc_pmr_el1(); 1146 1147 /* 1148 * Order memory updates w.r.t. PMR write, and ensure they're visible 1149 * before potential out of band interrupt trigger because of PMR update. 1150 * PMR system register writes are self-synchronizing, so no ISB required 1151 * thereafter. 1152 */ 1153 dsbishst(); 1154 write_icc_pmr_el1(mask); 1155 1156 return old_mask; 1157 } 1158