1/* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <neoverse_n1.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13/* Hardware handled coherency */ 14#if HW_ASSISTED_COHERENCY == 0 15#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled" 16#endif 17 18/* -------------------------------------------------- 19 * Errata Workaround for Neoverse N1 Errata 20 * This applies to revision r0p0 and r1p0 of Neoverse N1. 21 * Inputs: 22 * x0: variant[4:7] and revision[0:3] of current cpu. 23 * Shall clobber: x0-x17 24 * -------------------------------------------------- 25 */ 26func errata_n1_1043202_wa 27 /* Compare x0 against revision r1p0 */ 28 mov x17, x30 29 bl check_errata_1043202 30 cbz x0, 1f 31 32 /* Apply instruction patching sequence */ 33 ldr x0, =0x0 34 msr CPUPSELR_EL3, x0 35 ldr x0, =0xF3BF8F2F 36 msr CPUPOR_EL3, x0 37 ldr x0, =0xFFFFFFFF 38 msr CPUPMR_EL3, x0 39 ldr x0, =0x800200071 40 msr CPUPCR_EL3, x0 41 isb 421: 43 ret x17 44endfunc errata_n1_1043202_wa 45 46func check_errata_1043202 47 /* Applies to r0p0 and r1p0 */ 48 mov x1, #0x10 49 b cpu_rev_var_ls 50endfunc check_errata_1043202 51 52/* -------------------------------------------------- 53 * Disable speculative loads if Neoverse N1 supports 54 * SSBS. 55 * 56 * Shall clobber: x0. 57 * -------------------------------------------------- 58 */ 59func neoverse_n1_disable_speculative_loads 60 /* Check if the PE implements SSBS */ 61 mrs x0, id_aa64pfr1_el1 62 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) 63 b.eq 1f 64 65 /* Disable speculative loads */ 66 msr SSBS, xzr 67 isb 68 691: 70 ret 71endfunc neoverse_n1_disable_speculative_loads 72 73func neoverse_n1_reset_func 74 mov x19, x30 75 76 bl neoverse_n1_disable_speculative_loads 77 78 /* Forces all cacheable atomic instructions to be near */ 79 mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 80 orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 81 msr NEOVERSE_N1_CPUACTLR2_EL1, x0 82 isb 83 84 bl cpu_get_rev_var 85 mov x18, x0 86 87#if ERRATA_N1_1043202 88 mov x0, x18 89 bl errata_n1_1043202_wa 90#endif 91 92#if ENABLE_AMU 93 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 94 mrs x0, actlr_el3 95 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 96 msr actlr_el3, x0 97 isb 98 99 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 100 mrs x0, actlr_el2 101 orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT 102 msr actlr_el2, x0 103 isb 104 105 /* Enable group0 counters */ 106 mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK 107 msr CPUAMCNTENSET_EL0, x0 108 isb 109#endif 110 ret x19 111endfunc neoverse_n1_reset_func 112 113 /* --------------------------------------------- 114 * HW will do the cache maintenance while powering down 115 * --------------------------------------------- 116 */ 117func neoverse_n1_core_pwr_dwn 118 /* --------------------------------------------- 119 * Enable CPU power down bit in power control register 120 * --------------------------------------------- 121 */ 122 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 123 orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 124 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 125 isb 126 ret 127endfunc neoverse_n1_core_pwr_dwn 128 129#if REPORT_ERRATA 130/* 131 * Errata printing function for Neoverse N1. Must follow AAPCS. 132 */ 133func neoverse_n1_errata_report 134 stp x8, x30, [sp, #-16]! 135 136 bl cpu_get_rev_var 137 mov x8, x0 138 139 /* 140 * Report all errata. The revision-variant information is passed to 141 * checking functions of each errata. 142 */ 143 report_errata ERRATA_N1_1043202, neoverse_n1, 1043202 144 145 ldp x8, x30, [sp], #16 146 ret 147endfunc neoverse_n1_errata_report 148#endif 149 150 /* --------------------------------------------- 151 * This function provides neoverse_n1 specific 152 * register information for crash reporting. 153 * It needs to return with x6 pointing to 154 * a list of register names in ascii and 155 * x8 - x15 having values of registers to be 156 * reported. 157 * --------------------------------------------- 158 */ 159.section .rodata.neoverse_n1_regs, "aS" 160neoverse_n1_regs: /* The ascii list of register names to be reported */ 161 .asciz "cpuectlr_el1", "" 162 163func neoverse_n1_cpu_reg_dump 164 adr x6, neoverse_n1_regs 165 mrs x8, NEOVERSE_N1_CPUECTLR_EL1 166 ret 167endfunc neoverse_n1_cpu_reg_dump 168 169declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \ 170 neoverse_n1_reset_func, \ 171 neoverse_n1_core_pwr_dwn 172