1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <auth_mod.h> 11 #include <bl1.h> 12 #include <bl_common.h> 13 #include <console.h> 14 #include <debug.h> 15 #include <errata_report.h> 16 #include <platform.h> 17 #include <platform_def.h> 18 #include <smccc_helpers.h> 19 #include <utils.h> 20 #include <uuid.h> 21 #include "bl1_private.h" 22 23 /* BL1 Service UUID */ 24 DEFINE_SVC_UUID2(bl1_svc_uid, 25 0xd46739fd, 0xcb72, 0x9a4d, 0xb5, 0x75, 26 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a); 27 28 static void bl1_load_bl2(void); 29 30 /******************************************************************************* 31 * Helper utility to calculate the BL2 memory layout taking into consideration 32 * the BL1 RW data assuming that it is at the top of the memory layout. 33 ******************************************************************************/ 34 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, 35 meminfo_t *bl2_mem_layout) 36 { 37 assert(bl1_mem_layout != NULL); 38 assert(bl2_mem_layout != NULL); 39 40 /* 41 * Remove BL1 RW data from the scope of memory visible to BL2. 42 * This is assuming BL1 RW data is at the top of bl1_mem_layout. 43 */ 44 assert(BL1_RW_BASE > bl1_mem_layout->total_base); 45 bl2_mem_layout->total_base = bl1_mem_layout->total_base; 46 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; 47 48 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); 49 } 50 51 #if !ERROR_DEPRECATED 52 /******************************************************************************* 53 * Compatibility default implementation for deprecated API. This has a weak 54 * definition. Platform specific code can override it if it wishes to. 55 ******************************************************************************/ 56 #pragma weak bl1_init_bl2_mem_layout 57 58 /******************************************************************************* 59 * Function that takes a memory layout into which BL2 has been loaded and 60 * populates a new memory layout for BL2 that ensures that BL1's data sections 61 * resident in secure RAM are not visible to BL2. 62 ******************************************************************************/ 63 void bl1_init_bl2_mem_layout(const struct meminfo *bl1_mem_layout, 64 struct meminfo *bl2_mem_layout) 65 { 66 bl1_calc_bl2_mem_layout(bl1_mem_layout, bl2_mem_layout); 67 } 68 #endif 69 70 /******************************************************************************* 71 * Function to perform late architectural and platform specific initialization. 72 * It also queries the platform to load and run next BL image. Only called 73 * by the primary cpu after a cold boot. 74 ******************************************************************************/ 75 void bl1_main(void) 76 { 77 unsigned int image_id; 78 79 /* Announce our arrival */ 80 NOTICE(FIRMWARE_WELCOME_STR); 81 NOTICE("BL1: %s\n", version_string); 82 NOTICE("BL1: %s\n", build_message); 83 84 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, 85 (void *)BL1_RAM_LIMIT); 86 87 print_errata_status(); 88 89 #if ENABLE_ASSERTIONS 90 u_register_t val; 91 /* 92 * Ensure that MMU/Caches and coherency are turned on 93 */ 94 #ifdef AARCH32 95 val = read_sctlr(); 96 #else 97 val = read_sctlr_el3(); 98 #endif 99 assert(val & SCTLR_M_BIT); 100 assert(val & SCTLR_C_BIT); 101 assert(val & SCTLR_I_BIT); 102 /* 103 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the 104 * provided platform value 105 */ 106 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; 107 /* 108 * If CWG is zero, then no CWG information is available but we can 109 * at least check the platform value is less than the architectural 110 * maximum. 111 */ 112 if (val != 0) 113 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); 114 else 115 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); 116 #endif /* ENABLE_ASSERTIONS */ 117 118 /* Perform remaining generic architectural setup from EL3 */ 119 bl1_arch_setup(); 120 121 #if TRUSTED_BOARD_BOOT 122 /* Initialize authentication module */ 123 auth_mod_init(); 124 #endif /* TRUSTED_BOARD_BOOT */ 125 126 /* Perform platform setup in BL1. */ 127 bl1_platform_setup(); 128 129 /* Get the image id of next image to load and run. */ 130 image_id = bl1_plat_get_next_image_id(); 131 132 /* 133 * We currently interpret any image id other than 134 * BL2_IMAGE_ID as the start of firmware update. 135 */ 136 if (image_id == BL2_IMAGE_ID) 137 bl1_load_bl2(); 138 else 139 NOTICE("BL1-FWU: *******FWU Process Started*******\n"); 140 141 bl1_prepare_next_image(image_id); 142 143 console_flush(); 144 } 145 146 /******************************************************************************* 147 * This function locates and loads the BL2 raw binary image in the trusted SRAM. 148 * Called by the primary cpu after a cold boot. 149 * TODO: Add support for alternative image load mechanism e.g using virtio/elf 150 * loader etc. 151 ******************************************************************************/ 152 static void bl1_load_bl2(void) 153 { 154 image_desc_t *image_desc; 155 image_info_t *image_info; 156 int err; 157 158 /* Get the image descriptor */ 159 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); 160 assert(image_desc); 161 162 /* Get the image info */ 163 image_info = &image_desc->image_info; 164 INFO("BL1: Loading BL2\n"); 165 166 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID); 167 if (err) { 168 ERROR("Failure in pre image load handling of BL2 (%d)\n", err); 169 plat_error_handler(err); 170 } 171 172 err = load_auth_image(BL2_IMAGE_ID, image_info); 173 if (err) { 174 ERROR("Failed to load BL2 firmware.\n"); 175 plat_error_handler(err); 176 } 177 178 /* Allow platform to handle image information. */ 179 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID); 180 if (err) { 181 ERROR("Failure in post image load handling of BL2 (%d)\n", err); 182 plat_error_handler(err); 183 } 184 185 NOTICE("BL1: Booting BL2\n"); 186 } 187 188 /******************************************************************************* 189 * Function called just before handing over to the next BL to inform the user 190 * about the boot progress. In debug mode, also print details about the BL 191 * image's execution context. 192 ******************************************************************************/ 193 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info) 194 { 195 #ifdef AARCH32 196 NOTICE("BL1: Booting BL32\n"); 197 #else 198 NOTICE("BL1: Booting BL31\n"); 199 #endif /* AARCH32 */ 200 print_entry_point_info(bl_ep_info); 201 } 202 203 #if SPIN_ON_BL1_EXIT 204 void print_debug_loop_message(void) 205 { 206 NOTICE("BL1: Debug loop, spinning forever\n"); 207 NOTICE("BL1: Please connect the debugger to continue\n"); 208 } 209 #endif 210 211 /******************************************************************************* 212 * Top level handler for servicing BL1 SMCs. 213 ******************************************************************************/ 214 register_t bl1_smc_handler(unsigned int smc_fid, 215 register_t x1, 216 register_t x2, 217 register_t x3, 218 register_t x4, 219 void *cookie, 220 void *handle, 221 unsigned int flags) 222 { 223 224 #if TRUSTED_BOARD_BOOT 225 /* 226 * Dispatch FWU calls to FWU SMC handler and return its return 227 * value 228 */ 229 if (is_fwu_fid(smc_fid)) { 230 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie, 231 handle, flags); 232 } 233 #endif 234 235 switch (smc_fid) { 236 case BL1_SMC_CALL_COUNT: 237 SMC_RET1(handle, BL1_NUM_SMC_CALLS); 238 239 case BL1_SMC_UID: 240 SMC_UUID_RET(handle, bl1_svc_uid); 241 242 case BL1_SMC_VERSION: 243 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER); 244 245 default: 246 break; 247 } 248 249 WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid); 250 SMC_RET1(handle, SMC_UNK); 251 } 252 253 /******************************************************************************* 254 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI 255 * compliance when invoking bl1_smc_handler. 256 ******************************************************************************/ 257 register_t bl1_smc_wrapper(uint32_t smc_fid, 258 void *cookie, 259 void *handle, 260 unsigned int flags) 261 { 262 register_t x1, x2, x3, x4; 263 264 assert(handle); 265 266 get_smc_params_from_ctx(handle, x1, x2, x3, x4); 267 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 268 } 269