1# 2# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7JUNO_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ 8 drivers/arm/gic/v2/gicv2_main.c \ 9 drivers/arm/gic/v2/gicv2_helpers.c \ 10 plat/common/plat_gicv2.c \ 11 plat/arm/common/arm_gicv2.c 12 13JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \ 14 plat/arm/common/arm_cci.c 15 16JUNO_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 17 plat/arm/board/juno/juno_security.c \ 18 plat/arm/board/juno/juno_trng.c \ 19 plat/arm/common/arm_tzc400.c 20 21ifneq (${ENABLE_STACK_PROTECTOR}, 0) 22JUNO_SECURITY_SOURCES += plat/arm/board/juno/juno_stack_protector.c 23endif 24 25PLAT_INCLUDES := -Iplat/arm/board/juno/include 26 27PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S 28 29# Flag to enable support for AArch32 state on JUNO 30JUNO_AARCH32_EL3_RUNTIME := 0 31$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME)) 32$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME)) 33 34ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 35# Include BL32 in FIP 36NEED_BL32 := yes 37# BL31 is not required 38override BL31_SOURCES = 39 40# The BL32 needs to be built separately invoking the AARCH32 compiler and 41# be specifed via `BL32` build option. 42 ifneq (${ARCH}, aarch32) 43 override BL32_SOURCES = 44 endif 45endif 46 47ifeq (${ARCH},aarch64) 48BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 49 lib/cpus/aarch64/cortex_a57.S \ 50 lib/cpus/aarch64/cortex_a72.S \ 51 plat/arm/board/juno/juno_bl1_setup.c \ 52 plat/arm/board/juno/juno_err.c \ 53 ${JUNO_INTERCONNECT_SOURCES} \ 54 ${JUNO_SECURITY_SOURCES} 55 56BL2_SOURCES += plat/arm/board/juno/juno_err.c \ 57 plat/arm/board/juno/juno_bl2_setup.c \ 58 ${JUNO_SECURITY_SOURCES} 59 60BL2U_SOURCES += ${JUNO_SECURITY_SOURCES} 61 62BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 63 lib/cpus/aarch64/cortex_a57.S \ 64 lib/cpus/aarch64/cortex_a72.S \ 65 plat/arm/board/juno/juno_topology.c \ 66 ${JUNO_GIC_SOURCES} \ 67 ${JUNO_INTERCONNECT_SOURCES} \ 68 ${JUNO_SECURITY_SOURCES} 69endif 70 71# Errata workarounds for Cortex-A53: 72ERRATA_A53_826319 := 1 73ERRATA_A53_835769 := 1 74ERRATA_A53_836870 := 1 75ERRATA_A53_843419 := 1 76ERRATA_A53_855873 := 1 77 78# Errata workarounds for Cortex-A57: 79ERRATA_A57_806969 := 0 80ERRATA_A57_813419 := 1 81ERRATA_A57_813420 := 1 82ERRATA_A57_826974 := 1 83ERRATA_A57_826977 := 1 84ERRATA_A57_828024 := 1 85ERRATA_A57_829520 := 1 86ERRATA_A57_833471 := 1 87ERRATA_A57_859972 := 0 88 89# Errata workarounds for Cortex-A72: 90ERRATA_A72_859971 := 0 91 92# Enable option to skip L1 data cache flush during the Cortex-A57 cluster 93# power down sequence 94SKIP_A57_L1_FLUSH_PWR_DWN := 1 95 96# Disable the PSCI platform compatibility layer 97ENABLE_PLAT_COMPAT := 0 98 99# Enable memory map related constants optimisation 100ARM_BOARD_OPTIMISE_MEM := 1 101 102# Do not enable SVE 103ENABLE_SVE_FOR_NS := 0 104 105# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 106# SCP during power management operations and for SCP RAM Firmware transfer. 107CSS_USE_SCMI_SDS_DRIVER := 1 108 109include plat/arm/board/common/board_css.mk 110include plat/arm/common/arm_common.mk 111include plat/arm/soc/common/soc_css.mk 112include plat/arm/css/common/css_common.mk 113 114