1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <amu.h> 8 #include <arch.h> 9 #include <arch_helpers.h> 10 #include <assert.h> 11 #include <bl_common.h> 12 #include <context.h> 13 #include <context_mgmt.h> 14 #include <interrupt_mgmt.h> 15 #include <mpam.h> 16 #include <platform.h> 17 #include <platform_def.h> 18 #include <pubsub_events.h> 19 #include <smccc_helpers.h> 20 #include <spe.h> 21 #include <string.h> 22 #include <sve.h> 23 #include <utils.h> 24 25 26 /******************************************************************************* 27 * Context management library initialisation routine. This library is used by 28 * runtime services to share pointers to 'cpu_context' structures for the secure 29 * and non-secure states. Management of the structures and their associated 30 * memory is not done by the context management library e.g. the PSCI service 31 * manages the cpu context used for entry from and exit to the non-secure state. 32 * The Secure payload dispatcher service manages the context(s) corresponding to 33 * the secure state. It also uses this library to get access to the non-secure 34 * state cpu context pointers. 35 * Lastly, this library provides the api to make SP_EL3 point to the cpu context 36 * which will used for programming an entry into a lower EL. The same context 37 * will used to save state upon exception entry from that EL. 38 ******************************************************************************/ 39 void __init cm_init(void) 40 { 41 /* 42 * The context management library has only global data to intialize, but 43 * that will be done when the BSS is zeroed out 44 */ 45 } 46 47 /******************************************************************************* 48 * The following function initializes the cpu_context 'ctx' for 49 * first use, and sets the initial entrypoint state as specified by the 50 * entry_point_info structure. 51 * 52 * The security state to initialize is determined by the SECURE attribute 53 * of the entry_point_info. 54 * 55 * The EE and ST attributes are used to configure the endianess and secure 56 * timer availability for the new execution context. 57 * 58 * To prepare the register state for entry call cm_prepare_el3_exit() and 59 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to 60 * cm_e1_sysreg_context_restore(). 61 ******************************************************************************/ 62 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 63 { 64 unsigned int security_state; 65 uint32_t scr_el3, pmcr_el0; 66 el3_state_t *state; 67 gp_regs_t *gp_regs; 68 unsigned long sctlr_elx, actlr_elx; 69 70 assert(ctx); 71 72 security_state = GET_SECURITY_STATE(ep->h.attr); 73 74 /* Clear any residual register values from the context */ 75 zeromem(ctx, sizeof(*ctx)); 76 77 /* 78 * SCR_EL3 was initialised during reset sequence in macro 79 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 80 * affect the next EL. 81 * 82 * The following fields are initially set to zero and then updated to 83 * the required value depending on the state of the SPSR_EL3 and the 84 * Security state and entrypoint attributes of the next EL. 85 */ 86 scr_el3 = read_scr(); 87 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 88 SCR_ST_BIT | SCR_HCE_BIT); 89 /* 90 * SCR_NS: Set the security state of the next EL. 91 */ 92 if (security_state != SECURE) 93 scr_el3 |= SCR_NS_BIT; 94 /* 95 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 96 * Exception level as specified by SPSR. 97 */ 98 if (GET_RW(ep->spsr) == MODE_RW_64) 99 scr_el3 |= SCR_RW_BIT; 100 /* 101 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 102 * Secure timer registers to EL3, from AArch64 state only, if specified 103 * by the entrypoint attributes. 104 */ 105 if (EP_GET_ST(ep->h.attr)) 106 scr_el3 |= SCR_ST_BIT; 107 108 #if !HANDLE_EA_EL3_FIRST 109 /* 110 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External 111 * to EL3 when executing at a lower EL. When executing at EL3, External 112 * Aborts are taken to EL3. 113 */ 114 scr_el3 &= ~SCR_EA_BIT; 115 #endif 116 117 #if FAULT_INJECTION_SUPPORT 118 /* Enable fault injection from lower ELs */ 119 scr_el3 |= SCR_FIEN_BIT; 120 #endif 121 122 #ifdef IMAGE_BL31 123 /* 124 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ rounting as 125 * indicated by the interrupt routing model for BL31. 126 */ 127 scr_el3 |= get_scr_el3_from_routing_model(security_state); 128 #endif 129 130 /* 131 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 132 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 133 * next mode is Hyp. 134 */ 135 if ((GET_RW(ep->spsr) == MODE_RW_64 136 && GET_EL(ep->spsr) == MODE_EL2) 137 || (GET_RW(ep->spsr) != MODE_RW_64 138 && GET_M32(ep->spsr) == MODE32_hyp)) { 139 scr_el3 |= SCR_HCE_BIT; 140 } 141 142 /* 143 * Initialise SCTLR_EL1 to the reset value corresponding to the target 144 * execution state setting all fields rather than relying of the hw. 145 * Some fields have architecturally UNKNOWN reset values and these are 146 * set to zero. 147 * 148 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 149 * 150 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 151 * required by PSCI specification) 152 */ 153 sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0; 154 if (GET_RW(ep->spsr) == MODE_RW_64) 155 sctlr_elx |= SCTLR_EL1_RES1; 156 else { 157 /* 158 * If the target execution state is AArch32 then the following 159 * fields need to be set. 160 * 161 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 162 * instructions are not trapped to EL1. 163 * 164 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 165 * instructions are not trapped to EL1. 166 * 167 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 168 * CP15DMB, CP15DSB, and CP15ISB instructions. 169 */ 170 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 171 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 172 } 173 174 /* 175 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 176 * and other EL2 registers are set up by cm_preapre_ns_entry() as they 177 * are not part of the stored cpu_context. 178 */ 179 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 180 181 /* 182 * Base the context ACTLR_EL1 on the current value, as it is 183 * implementation defined. The context restore process will write 184 * the value from the context to the actual register and can cause 185 * problems for processor cores that don't expect certain bits to 186 * be zero. 187 */ 188 actlr_elx = read_actlr_el1(); 189 write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 190 191 if (security_state == SECURE) { 192 /* 193 * Initialise PMCR_EL0 for secure context only, setting all 194 * fields rather than relying on hw. Some fields are 195 * architecturally UNKNOWN on reset. 196 * 197 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that 198 * is recorded in PMOVSCLR_EL0[31], occurs on the increment 199 * that changes PMCCNTR_EL0[63] from 1 to 0. 200 * 201 * PMCR_EL0.DP: Set to one so that the cycle counter, 202 * PMCCNTR_EL0 does not count when event counting is prohibited. 203 * 204 * PMCR_EL0.X: Set to zero to disable export of events. 205 * 206 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0 207 * counts on every clock cycle. 208 */ 209 pmcr_el0 = ((PMCR_EL0_RESET_VAL | PMCR_EL0_LC_BIT 210 | PMCR_EL0_DP_BIT) 211 & ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)); 212 write_ctx_reg(get_sysregs_ctx(ctx), CTX_PMCR_EL0, pmcr_el0); 213 } 214 215 /* Populate EL3 state so that we've the right context before doing ERET */ 216 state = get_el3state_ctx(ctx); 217 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 218 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 219 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 220 221 /* 222 * Store the X0-X7 value from the entrypoint into the context 223 * Use memcpy as we are in control of the layout of the structures 224 */ 225 gp_regs = get_gpregs_ctx(ctx); 226 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 227 } 228 229 /******************************************************************************* 230 * Enable architecture extensions on first entry to Non-secure world. 231 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 232 * it is zero. 233 ******************************************************************************/ 234 static void enable_extensions_nonsecure(int el2_unused) 235 { 236 #if IMAGE_BL31 237 #if ENABLE_SPE_FOR_LOWER_ELS 238 spe_enable(el2_unused); 239 #endif 240 241 #if ENABLE_AMU 242 amu_enable(el2_unused); 243 #endif 244 245 #if ENABLE_SVE_FOR_NS 246 sve_enable(el2_unused); 247 #endif 248 249 #if ENABLE_MPAM_FOR_LOWER_ELS 250 mpam_enable(el2_unused); 251 #endif 252 #endif 253 } 254 255 /******************************************************************************* 256 * The following function initializes the cpu_context for a CPU specified by 257 * its `cpu_idx` for first use, and sets the initial entrypoint state as 258 * specified by the entry_point_info structure. 259 ******************************************************************************/ 260 void cm_init_context_by_index(unsigned int cpu_idx, 261 const entry_point_info_t *ep) 262 { 263 cpu_context_t *ctx; 264 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 265 cm_setup_context(ctx, ep); 266 } 267 268 /******************************************************************************* 269 * The following function initializes the cpu_context for the current CPU 270 * for first use, and sets the initial entrypoint state as specified by the 271 * entry_point_info structure. 272 ******************************************************************************/ 273 void cm_init_my_context(const entry_point_info_t *ep) 274 { 275 cpu_context_t *ctx; 276 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 277 cm_setup_context(ctx, ep); 278 } 279 280 /******************************************************************************* 281 * Prepare the CPU system registers for first entry into secure or normal world 282 * 283 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 284 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 285 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 286 * For all entries, the EL1 registers are initialized from the cpu_context 287 ******************************************************************************/ 288 void cm_prepare_el3_exit(uint32_t security_state) 289 { 290 uint32_t sctlr_elx, scr_el3, mdcr_el2; 291 cpu_context_t *ctx = cm_get_context(security_state); 292 int el2_unused = 0; 293 uint64_t hcr_el2 = 0; 294 295 assert(ctx); 296 297 if (security_state == NON_SECURE) { 298 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 299 if (scr_el3 & SCR_HCE_BIT) { 300 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 301 sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), 302 CTX_SCTLR_EL1); 303 sctlr_elx &= SCTLR_EE_BIT; 304 sctlr_elx |= SCTLR_EL2_RES1; 305 write_sctlr_el2(sctlr_elx); 306 } else if (EL_IMPLEMENTED(2)) { 307 el2_unused = 1; 308 309 /* 310 * EL2 present but unused, need to disable safely. 311 * SCTLR_EL2 can be ignored in this case. 312 * 313 * Set EL2 register width appropriately: Set HCR_EL2 314 * field to match SCR_EL3.RW. 315 */ 316 if (scr_el3 & SCR_RW_BIT) 317 hcr_el2 |= HCR_RW_BIT; 318 319 /* 320 * For Armv8.3 pointer authentication feature, disable 321 * traps to EL2 when accessing key registers or using 322 * pointer authentication instructions from lower ELs. 323 */ 324 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 325 326 write_hcr_el2(hcr_el2); 327 328 /* 329 * Initialise CPTR_EL2 setting all fields rather than 330 * relying on the hw. All fields have architecturally 331 * UNKNOWN reset values. 332 * 333 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 334 * accesses to the CPACR_EL1 or CPACR from both 335 * Execution states do not trap to EL2. 336 * 337 * CPTR_EL2.TTA: Set to zero so that Non-secure System 338 * register accesses to the trace registers from both 339 * Execution states do not trap to EL2. 340 * 341 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 342 * to SIMD and floating-point functionality from both 343 * Execution states do not trap to EL2. 344 */ 345 write_cptr_el2(CPTR_EL2_RESET_VAL & 346 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 347 | CPTR_EL2_TFP_BIT)); 348 349 /* 350 * Initiliase CNTHCTL_EL2. All fields are 351 * architecturally UNKNOWN on reset and are set to zero 352 * except for field(s) listed below. 353 * 354 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to 355 * Hyp mode of Non-secure EL0 and EL1 accesses to the 356 * physical timer registers. 357 * 358 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 359 * Hyp mode of Non-secure EL0 and EL1 accesses to the 360 * physical counter registers. 361 */ 362 write_cnthctl_el2(CNTHCTL_RESET_VAL | 363 EL1PCEN_BIT | EL1PCTEN_BIT); 364 365 /* 366 * Initialise CNTVOFF_EL2 to zero as it resets to an 367 * architecturally UNKNOWN value. 368 */ 369 write_cntvoff_el2(0); 370 371 /* 372 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 373 * MPIDR_EL1 respectively. 374 */ 375 write_vpidr_el2(read_midr_el1()); 376 write_vmpidr_el2(read_mpidr_el1()); 377 378 /* 379 * Initialise VTTBR_EL2. All fields are architecturally 380 * UNKNOWN on reset. 381 * 382 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 383 * 2 address translation is disabled, cache maintenance 384 * operations depend on the VMID. 385 * 386 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 387 * translation is disabled. 388 */ 389 write_vttbr_el2(VTTBR_RESET_VAL & 390 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 391 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 392 393 /* 394 * Initialise MDCR_EL2, setting all fields rather than 395 * relying on hw. Some fields are architecturally 396 * UNKNOWN on reset. 397 * 398 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 399 * EL1 System register accesses to the Debug ROM 400 * registers are not trapped to EL2. 401 * 402 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 403 * System register accesses to the powerdown debug 404 * registers are not trapped to EL2. 405 * 406 * MDCR_EL2.TDA: Set to zero so that System register 407 * accesses to the debug registers do not trap to EL2. 408 * 409 * MDCR_EL2.TDE: Set to zero so that debug exceptions 410 * are not routed to EL2. 411 * 412 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 413 * Monitors. 414 * 415 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 416 * EL1 accesses to all Performance Monitors registers 417 * are not trapped to EL2. 418 * 419 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 420 * and EL1 accesses to the PMCR_EL0 or PMCR are not 421 * trapped to EL2. 422 * 423 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 424 * architecturally-defined reset value. 425 */ 426 mdcr_el2 = ((MDCR_EL2_RESET_VAL | 427 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 428 >> PMCR_EL0_N_SHIFT)) & 429 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT 430 | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT 431 | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT 432 | MDCR_EL2_TPMCR_BIT)); 433 434 write_mdcr_el2(mdcr_el2); 435 436 /* 437 * Initialise HSTR_EL2. All fields are architecturally 438 * UNKNOWN on reset. 439 * 440 * HSTR_EL2.T<n>: Set all these fields to zero so that 441 * Non-secure EL0 or EL1 accesses to System registers 442 * do not trap to EL2. 443 */ 444 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 445 /* 446 * Initialise CNTHP_CTL_EL2. All fields are 447 * architecturally UNKNOWN on reset. 448 * 449 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 450 * physical timer and prevent timer interrupts. 451 */ 452 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 453 ~(CNTHP_CTL_ENABLE_BIT)); 454 } 455 enable_extensions_nonsecure(el2_unused); 456 } 457 458 cm_el1_sysregs_context_restore(security_state); 459 cm_set_next_eret_context(security_state); 460 } 461 462 /******************************************************************************* 463 * The next four functions are used by runtime services to save and restore 464 * EL1 context on the 'cpu_context' structure for the specified security 465 * state. 466 ******************************************************************************/ 467 void cm_el1_sysregs_context_save(uint32_t security_state) 468 { 469 cpu_context_t *ctx; 470 471 ctx = cm_get_context(security_state); 472 assert(ctx); 473 474 el1_sysregs_context_save(get_sysregs_ctx(ctx)); 475 476 #if IMAGE_BL31 477 if (security_state == SECURE) 478 PUBLISH_EVENT(cm_exited_secure_world); 479 else 480 PUBLISH_EVENT(cm_exited_normal_world); 481 #endif 482 } 483 484 void cm_el1_sysregs_context_restore(uint32_t security_state) 485 { 486 cpu_context_t *ctx; 487 488 ctx = cm_get_context(security_state); 489 assert(ctx); 490 491 el1_sysregs_context_restore(get_sysregs_ctx(ctx)); 492 493 #if IMAGE_BL31 494 if (security_state == SECURE) 495 PUBLISH_EVENT(cm_entering_secure_world); 496 else 497 PUBLISH_EVENT(cm_entering_normal_world); 498 #endif 499 } 500 501 /******************************************************************************* 502 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 503 * given security state with the given entrypoint 504 ******************************************************************************/ 505 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 506 { 507 cpu_context_t *ctx; 508 el3_state_t *state; 509 510 ctx = cm_get_context(security_state); 511 assert(ctx); 512 513 /* Populate EL3 state so that ERET jumps to the correct entry */ 514 state = get_el3state_ctx(ctx); 515 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 516 } 517 518 /******************************************************************************* 519 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 520 * pertaining to the given security state 521 ******************************************************************************/ 522 void cm_set_elr_spsr_el3(uint32_t security_state, 523 uintptr_t entrypoint, uint32_t spsr) 524 { 525 cpu_context_t *ctx; 526 el3_state_t *state; 527 528 ctx = cm_get_context(security_state); 529 assert(ctx); 530 531 /* Populate EL3 state so that ERET jumps to the correct entry */ 532 state = get_el3state_ctx(ctx); 533 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 534 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 535 } 536 537 /******************************************************************************* 538 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 539 * pertaining to the given security state using the value and bit position 540 * specified in the parameters. It preserves all other bits. 541 ******************************************************************************/ 542 void cm_write_scr_el3_bit(uint32_t security_state, 543 uint32_t bit_pos, 544 uint32_t value) 545 { 546 cpu_context_t *ctx; 547 el3_state_t *state; 548 uint32_t scr_el3; 549 550 ctx = cm_get_context(security_state); 551 assert(ctx); 552 553 /* Ensure that the bit position is a valid one */ 554 assert((1 << bit_pos) & SCR_VALID_BIT_MASK); 555 556 /* Ensure that the 'value' is only a bit wide */ 557 assert(value <= 1); 558 559 /* 560 * Get the SCR_EL3 value from the cpu context, clear the desired bit 561 * and set it to its new value. 562 */ 563 state = get_el3state_ctx(ctx); 564 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 565 scr_el3 &= ~(1 << bit_pos); 566 scr_el3 |= value << bit_pos; 567 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 568 } 569 570 /******************************************************************************* 571 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 572 * given security state. 573 ******************************************************************************/ 574 uint32_t cm_get_scr_el3(uint32_t security_state) 575 { 576 cpu_context_t *ctx; 577 el3_state_t *state; 578 579 ctx = cm_get_context(security_state); 580 assert(ctx); 581 582 /* Populate EL3 state so that ERET jumps to the correct entry */ 583 state = get_el3state_ctx(ctx); 584 return read_ctx_reg(state, CTX_SCR_EL3); 585 } 586 587 /******************************************************************************* 588 * This function is used to program the context that's used for exception 589 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 590 * the required security state 591 ******************************************************************************/ 592 void cm_set_next_eret_context(uint32_t security_state) 593 { 594 cpu_context_t *ctx; 595 596 ctx = cm_get_context(security_state); 597 assert(ctx); 598 599 cm_set_next_context(ctx); 600 } 601