1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_H 8 #define ARCH_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * MIDR bit definitions 14 ******************************************************************************/ 15 #define MIDR_IMPL_MASK U(0xff) 16 #define MIDR_IMPL_SHIFT U(0x18) 17 #define MIDR_VAR_SHIFT U(20) 18 #define MIDR_VAR_BITS U(4) 19 #define MIDR_VAR_MASK U(0xf) 20 #define MIDR_REV_SHIFT U(0) 21 #define MIDR_REV_BITS U(4) 22 #define MIDR_REV_MASK U(0xf) 23 #define MIDR_PN_MASK U(0xfff) 24 #define MIDR_PN_SHIFT U(0x4) 25 26 /******************************************************************************* 27 * MPIDR macros 28 ******************************************************************************/ 29 #define MPIDR_MT_MASK (ULL(1) << 24) 30 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 31 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 32 #define MPIDR_AFFINITY_BITS U(8) 33 #define MPIDR_AFFLVL_MASK ULL(0xff) 34 #define MPIDR_AFF0_SHIFT U(0) 35 #define MPIDR_AFF1_SHIFT U(8) 36 #define MPIDR_AFF2_SHIFT U(16) 37 #define MPIDR_AFF3_SHIFT U(32) 38 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 39 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 40 #define MPIDR_AFFLVL_SHIFT U(3) 41 #define MPIDR_AFFLVL0 ULL(0x0) 42 #define MPIDR_AFFLVL1 ULL(0x1) 43 #define MPIDR_AFFLVL2 ULL(0x2) 44 #define MPIDR_AFFLVL3 ULL(0x3) 45 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 46 #define MPIDR_AFFLVL0_VAL(mpidr) \ 47 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 48 #define MPIDR_AFFLVL1_VAL(mpidr) \ 49 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 50 #define MPIDR_AFFLVL2_VAL(mpidr) \ 51 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 52 #define MPIDR_AFFLVL3_VAL(mpidr) \ 53 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 54 /* 55 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 56 * add one while using this macro to define array sizes. 57 * TODO: Support only the first 3 affinity levels for now. 58 */ 59 #define MPIDR_MAX_AFFLVL U(2) 60 61 #define MPID_MASK (MPIDR_MT_MASK | \ 62 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 66 67 #define MPIDR_AFF_ID(mpid, n) \ 68 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 69 70 /* 71 * An invalid MPID. This value can be used by functions that return an MPID to 72 * indicate an error. 73 */ 74 #define INVALID_MPID U(0xFFFFFFFF) 75 76 /******************************************************************************* 77 * Definitions for CPU system register interface to GICv3 78 ******************************************************************************/ 79 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 80 #define ICC_SGI1R S3_0_C12_C11_5 81 #define ICC_SRE_EL1 S3_0_C12_C12_5 82 #define ICC_SRE_EL2 S3_4_C12_C9_5 83 #define ICC_SRE_EL3 S3_6_C12_C12_5 84 #define ICC_CTLR_EL1 S3_0_C12_C12_4 85 #define ICC_CTLR_EL3 S3_6_C12_C12_4 86 #define ICC_PMR_EL1 S3_0_C4_C6_0 87 #define ICC_RPR_EL1 S3_0_C12_C11_3 88 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 89 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 90 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 91 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 92 #define ICC_IAR0_EL1 S3_0_c12_c8_0 93 #define ICC_IAR1_EL1 S3_0_c12_c12_0 94 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 95 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 96 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 97 98 /******************************************************************************* 99 * Generic timer memory mapped registers & offsets 100 ******************************************************************************/ 101 #define CNTCR_OFF U(0x000) 102 #define CNTFID_OFF U(0x020) 103 104 #define CNTCR_EN (U(1) << 0) 105 #define CNTCR_HDBG (U(1) << 1) 106 #define CNTCR_FCREQ(x) ((x) << 8) 107 108 /******************************************************************************* 109 * System register bit definitions 110 ******************************************************************************/ 111 /* CLIDR definitions */ 112 #define LOUIS_SHIFT U(21) 113 #define LOC_SHIFT U(24) 114 #define CLIDR_FIELD_WIDTH U(3) 115 116 /* CSSELR definitions */ 117 #define LEVEL_SHIFT U(1) 118 119 /* Data cache set/way op type defines */ 120 #define DCISW U(0x0) 121 #define DCCISW U(0x1) 122 #if ERRATA_A53_827319 123 #define DCCSW DCCISW 124 #else 125 #define DCCSW U(0x2) 126 #endif 127 128 /* ID_AA64PFR0_EL1 definitions */ 129 #define ID_AA64PFR0_EL0_SHIFT U(0) 130 #define ID_AA64PFR0_EL1_SHIFT U(4) 131 #define ID_AA64PFR0_EL2_SHIFT U(8) 132 #define ID_AA64PFR0_EL3_SHIFT U(12) 133 #define ID_AA64PFR0_AMU_SHIFT U(44) 134 #define ID_AA64PFR0_AMU_LENGTH U(4) 135 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 136 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 137 #define ID_AA64PFR0_SVE_SHIFT U(32) 138 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 139 #define ID_AA64PFR0_SVE_LENGTH U(4) 140 #define ID_AA64PFR0_MPAM_SHIFT U(40) 141 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 142 #define ID_AA64PFR0_DIT_SHIFT U(48) 143 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 144 #define ID_AA64PFR0_DIT_LENGTH U(4) 145 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 146 #define ID_AA64PFR0_CSV2_SHIFT U(56) 147 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 148 #define ID_AA64PFR0_CSV2_LENGTH U(4) 149 150 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 151 #define ID_AA64DFR0_PMS_SHIFT U(32) 152 #define ID_AA64DFR0_PMS_LENGTH U(4) 153 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 154 155 #define EL_IMPL_NONE ULL(0) 156 #define EL_IMPL_A64ONLY ULL(1) 157 #define EL_IMPL_A64_A32 ULL(2) 158 159 #define ID_AA64PFR0_GIC_SHIFT U(24) 160 #define ID_AA64PFR0_GIC_WIDTH U(4) 161 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 162 163 /* ID_AA64ISAR1_EL1 definitions */ 164 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 165 #define ID_AA64ISAR1_GPI_SHIFT U(28) 166 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 167 #define ID_AA64ISAR1_GPA_SHIFT U(24) 168 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 169 #define ID_AA64ISAR1_API_SHIFT U(8) 170 #define ID_AA64ISAR1_API_MASK ULL(0xf) 171 #define ID_AA64ISAR1_APA_SHIFT U(4) 172 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 173 174 /* ID_AA64MMFR0_EL1 definitions */ 175 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 176 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 177 178 #define PARANGE_0000 U(32) 179 #define PARANGE_0001 U(36) 180 #define PARANGE_0010 U(40) 181 #define PARANGE_0011 U(42) 182 #define PARANGE_0100 U(44) 183 #define PARANGE_0101 U(48) 184 #define PARANGE_0110 U(52) 185 186 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 187 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 188 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 189 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 190 191 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 192 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 193 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 194 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 195 196 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 197 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 198 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 199 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 200 201 /* ID_AA64MMFR2_EL1 definitions */ 202 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 203 204 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 205 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 206 207 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 208 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 209 210 /* ID_AA64PFR1_EL1 definitions */ 211 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 212 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 213 214 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 215 216 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 217 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 218 219 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 220 221 /* ID_PFR1_EL1 definitions */ 222 #define ID_PFR1_VIRTEXT_SHIFT U(12) 223 #define ID_PFR1_VIRTEXT_MASK U(0xf) 224 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 225 & ID_PFR1_VIRTEXT_MASK) 226 227 /* SCTLR definitions */ 228 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 229 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 230 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 231 232 #define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 233 (U(1) << 22) | (U(1) << 20) | (U(1) << 11)) 234 #define SCTLR_AARCH32_EL1_RES1 \ 235 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 236 (U(1) << 4) | (U(1) << 3)) 237 238 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 239 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 240 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 241 242 #define SCTLR_M_BIT (ULL(1) << 0) 243 #define SCTLR_A_BIT (ULL(1) << 1) 244 #define SCTLR_C_BIT (ULL(1) << 2) 245 #define SCTLR_SA_BIT (ULL(1) << 3) 246 #define SCTLR_SA0_BIT (ULL(1) << 4) 247 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 248 #define SCTLR_ITD_BIT (ULL(1) << 7) 249 #define SCTLR_SED_BIT (ULL(1) << 8) 250 #define SCTLR_UMA_BIT (ULL(1) << 9) 251 #define SCTLR_I_BIT (ULL(1) << 12) 252 #define SCTLR_V_BIT (ULL(1) << 13) 253 #define SCTLR_DZE_BIT (ULL(1) << 14) 254 #define SCTLR_UCT_BIT (ULL(1) << 15) 255 #define SCTLR_NTWI_BIT (ULL(1) << 16) 256 #define SCTLR_NTWE_BIT (ULL(1) << 18) 257 #define SCTLR_WXN_BIT (ULL(1) << 19) 258 #define SCTLR_UWXN_BIT (ULL(1) << 20) 259 #define SCTLR_IESB_BIT (ULL(1) << 21) 260 #define SCTLR_E0E_BIT (ULL(1) << 24) 261 #define SCTLR_EE_BIT (ULL(1) << 25) 262 #define SCTLR_UCI_BIT (ULL(1) << 26) 263 #define SCTLR_EnIA_BIT (ULL(1) << 31) 264 #define SCTLR_BT0_BIT (ULL(1) << 35) 265 #define SCTLR_BT1_BIT (ULL(1) << 36) 266 #define SCTLR_BT_BIT (ULL(1) << 36) 267 #define SCTLR_DSSBS_BIT (ULL(1) << 44) 268 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 269 270 /* CPACR_El1 definitions */ 271 #define CPACR_EL1_FPEN(x) ((x) << 20) 272 #define CPACR_EL1_FP_TRAP_EL0 U(0x1) 273 #define CPACR_EL1_FP_TRAP_ALL U(0x2) 274 #define CPACR_EL1_FP_TRAP_NONE U(0x3) 275 276 /* SCR definitions */ 277 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 278 #define SCR_FIEN_BIT (U(1) << 21) 279 #define SCR_API_BIT (U(1) << 17) 280 #define SCR_APK_BIT (U(1) << 16) 281 #define SCR_TWE_BIT (U(1) << 13) 282 #define SCR_TWI_BIT (U(1) << 12) 283 #define SCR_ST_BIT (U(1) << 11) 284 #define SCR_RW_BIT (U(1) << 10) 285 #define SCR_SIF_BIT (U(1) << 9) 286 #define SCR_HCE_BIT (U(1) << 8) 287 #define SCR_SMD_BIT (U(1) << 7) 288 #define SCR_EA_BIT (U(1) << 3) 289 #define SCR_FIQ_BIT (U(1) << 2) 290 #define SCR_IRQ_BIT (U(1) << 1) 291 #define SCR_NS_BIT (U(1) << 0) 292 #define SCR_VALID_BIT_MASK U(0x2f8f) 293 #define SCR_RESET_VAL SCR_RES1_BITS 294 295 /* MDCR_EL3 definitions */ 296 #define MDCR_SPD32(x) ((x) << 14) 297 #define MDCR_SPD32_LEGACY ULL(0x0) 298 #define MDCR_SPD32_DISABLE ULL(0x2) 299 #define MDCR_SPD32_ENABLE ULL(0x3) 300 #define MDCR_SDD_BIT (ULL(1) << 16) 301 #define MDCR_NSPB(x) ((x) << 12) 302 #define MDCR_NSPB_EL1 ULL(0x3) 303 #define MDCR_TDOSA_BIT (ULL(1) << 10) 304 #define MDCR_TDA_BIT (ULL(1) << 9) 305 #define MDCR_TPM_BIT (ULL(1) << 6) 306 #define MDCR_SCCD_BIT (ULL(1) << 23) 307 #define MDCR_EL3_RESET_VAL ULL(0x0) 308 309 /* MDCR_EL2 definitions */ 310 #define MDCR_EL2_TPMS (U(1) << 14) 311 #define MDCR_EL2_E2PB(x) ((x) << 12) 312 #define MDCR_EL2_E2PB_EL1 U(0x3) 313 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 314 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 315 #define MDCR_EL2_TDA_BIT (U(1) << 9) 316 #define MDCR_EL2_TDE_BIT (U(1) << 8) 317 #define MDCR_EL2_HPME_BIT (U(1) << 7) 318 #define MDCR_EL2_TPM_BIT (U(1) << 6) 319 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 320 #define MDCR_EL2_RESET_VAL U(0x0) 321 322 /* HSTR_EL2 definitions */ 323 #define HSTR_EL2_RESET_VAL U(0x0) 324 #define HSTR_EL2_T_MASK U(0xff) 325 326 /* CNTHP_CTL_EL2 definitions */ 327 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 328 #define CNTHP_CTL_RESET_VAL U(0x0) 329 330 /* VTTBR_EL2 definitions */ 331 #define VTTBR_RESET_VAL ULL(0x0) 332 #define VTTBR_VMID_MASK ULL(0xff) 333 #define VTTBR_VMID_SHIFT U(48) 334 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 335 #define VTTBR_BADDR_SHIFT U(0) 336 337 /* HCR definitions */ 338 #define HCR_API_BIT (ULL(1) << 41) 339 #define HCR_APK_BIT (ULL(1) << 40) 340 #define HCR_TGE_BIT (ULL(1) << 27) 341 #define HCR_RW_SHIFT U(31) 342 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 343 #define HCR_AMO_BIT (ULL(1) << 5) 344 #define HCR_IMO_BIT (ULL(1) << 4) 345 #define HCR_FMO_BIT (ULL(1) << 3) 346 347 /* ISR definitions */ 348 #define ISR_A_SHIFT U(8) 349 #define ISR_I_SHIFT U(7) 350 #define ISR_F_SHIFT U(6) 351 352 /* CNTHCTL_EL2 definitions */ 353 #define CNTHCTL_RESET_VAL U(0x0) 354 #define EVNTEN_BIT (U(1) << 2) 355 #define EL1PCEN_BIT (U(1) << 1) 356 #define EL1PCTEN_BIT (U(1) << 0) 357 358 /* CNTKCTL_EL1 definitions */ 359 #define EL0PTEN_BIT (U(1) << 9) 360 #define EL0VTEN_BIT (U(1) << 8) 361 #define EL0PCTEN_BIT (U(1) << 0) 362 #define EL0VCTEN_BIT (U(1) << 1) 363 #define EVNTEN_BIT (U(1) << 2) 364 #define EVNTDIR_BIT (U(1) << 3) 365 #define EVNTI_SHIFT U(4) 366 #define EVNTI_MASK U(0xf) 367 368 /* CPTR_EL3 definitions */ 369 #define TCPAC_BIT (U(1) << 31) 370 #define TAM_BIT (U(1) << 30) 371 #define TTA_BIT (U(1) << 20) 372 #define TFP_BIT (U(1) << 10) 373 #define CPTR_EZ_BIT (U(1) << 8) 374 #define CPTR_EL3_RESET_VAL U(0x0) 375 376 /* CPTR_EL2 definitions */ 377 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 378 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 379 #define CPTR_EL2_TAM_BIT (U(1) << 30) 380 #define CPTR_EL2_TTA_BIT (U(1) << 20) 381 #define CPTR_EL2_TFP_BIT (U(1) << 10) 382 #define CPTR_EL2_TZ_BIT (U(1) << 8) 383 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 384 385 /* CPSR/SPSR definitions */ 386 #define DAIF_FIQ_BIT (U(1) << 0) 387 #define DAIF_IRQ_BIT (U(1) << 1) 388 #define DAIF_ABT_BIT (U(1) << 2) 389 #define DAIF_DBG_BIT (U(1) << 3) 390 #define SPSR_DAIF_SHIFT U(6) 391 #define SPSR_DAIF_MASK U(0xf) 392 393 #define SPSR_AIF_SHIFT U(6) 394 #define SPSR_AIF_MASK U(0x7) 395 396 #define SPSR_E_SHIFT U(9) 397 #define SPSR_E_MASK U(0x1) 398 #define SPSR_E_LITTLE U(0x0) 399 #define SPSR_E_BIG U(0x1) 400 401 #define SPSR_T_SHIFT U(5) 402 #define SPSR_T_MASK U(0x1) 403 #define SPSR_T_ARM U(0x0) 404 #define SPSR_T_THUMB U(0x1) 405 406 #define SPSR_M_SHIFT U(4) 407 #define SPSR_M_MASK U(0x1) 408 #define SPSR_M_AARCH64 U(0x0) 409 #define SPSR_M_AARCH32 U(0x1) 410 411 #define DISABLE_ALL_EXCEPTIONS \ 412 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 413 414 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 415 416 /* 417 * RMR_EL3 definitions 418 */ 419 #define RMR_EL3_RR_BIT (U(1) << 1) 420 #define RMR_EL3_AA64_BIT (U(1) << 0) 421 422 /* 423 * HI-VECTOR address for AArch32 state 424 */ 425 #define HI_VECTOR_BASE U(0xFFFF0000) 426 427 /* 428 * TCR defintions 429 */ 430 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 431 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 432 #define TCR_EL1_IPS_SHIFT U(32) 433 #define TCR_EL2_PS_SHIFT U(16) 434 #define TCR_EL3_PS_SHIFT U(16) 435 436 #define TCR_TxSZ_MIN ULL(16) 437 #define TCR_TxSZ_MAX ULL(39) 438 #define TCR_TxSZ_MAX_TTST ULL(48) 439 440 #define TCR_T0SZ_SHIFT U(0) 441 #define TCR_T1SZ_SHIFT U(16) 442 443 /* (internal) physical address size bits in EL3/EL1 */ 444 #define TCR_PS_BITS_4GB ULL(0x0) 445 #define TCR_PS_BITS_64GB ULL(0x1) 446 #define TCR_PS_BITS_1TB ULL(0x2) 447 #define TCR_PS_BITS_4TB ULL(0x3) 448 #define TCR_PS_BITS_16TB ULL(0x4) 449 #define TCR_PS_BITS_256TB ULL(0x5) 450 451 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 452 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 453 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 454 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 455 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 456 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 457 458 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 459 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 460 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 461 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 462 463 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 464 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 465 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 466 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 467 468 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 469 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 470 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 471 472 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 473 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 474 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 475 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 476 477 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 478 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 479 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 480 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 481 482 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 483 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 484 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 485 486 #define TCR_TG0_SHIFT U(14) 487 #define TCR_TG0_MASK ULL(3) 488 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 489 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 490 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 491 492 #define TCR_TG1_SHIFT U(30) 493 #define TCR_TG1_MASK ULL(3) 494 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 495 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 496 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 497 498 #define TCR_EPD0_BIT (ULL(1) << 7) 499 #define TCR_EPD1_BIT (ULL(1) << 23) 500 501 #define MODE_SP_SHIFT U(0x0) 502 #define MODE_SP_MASK U(0x1) 503 #define MODE_SP_EL0 U(0x0) 504 #define MODE_SP_ELX U(0x1) 505 506 #define MODE_RW_SHIFT U(0x4) 507 #define MODE_RW_MASK U(0x1) 508 #define MODE_RW_64 U(0x0) 509 #define MODE_RW_32 U(0x1) 510 511 #define MODE_EL_SHIFT U(0x2) 512 #define MODE_EL_MASK U(0x3) 513 #define MODE_EL3 U(0x3) 514 #define MODE_EL2 U(0x2) 515 #define MODE_EL1 U(0x1) 516 #define MODE_EL0 U(0x0) 517 518 #define MODE32_SHIFT U(0) 519 #define MODE32_MASK U(0xf) 520 #define MODE32_usr U(0x0) 521 #define MODE32_fiq U(0x1) 522 #define MODE32_irq U(0x2) 523 #define MODE32_svc U(0x3) 524 #define MODE32_mon U(0x6) 525 #define MODE32_abt U(0x7) 526 #define MODE32_hyp U(0xa) 527 #define MODE32_und U(0xb) 528 #define MODE32_sys U(0xf) 529 530 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 531 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 532 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 533 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 534 535 #define SPSR_64(el, sp, daif) \ 536 ((MODE_RW_64 << MODE_RW_SHIFT) | \ 537 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 538 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 539 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) 540 541 #define SPSR_MODE32(mode, isa, endian, aif) \ 542 ((MODE_RW_32 << MODE_RW_SHIFT) | \ 543 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 544 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 545 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 546 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) 547 548 /* 549 * TTBR Definitions 550 */ 551 #define TTBR_CNP_BIT ULL(0x1) 552 553 /* 554 * CTR_EL0 definitions 555 */ 556 #define CTR_CWG_SHIFT U(24) 557 #define CTR_CWG_MASK U(0xf) 558 #define CTR_ERG_SHIFT U(20) 559 #define CTR_ERG_MASK U(0xf) 560 #define CTR_DMINLINE_SHIFT U(16) 561 #define CTR_DMINLINE_MASK U(0xf) 562 #define CTR_L1IP_SHIFT U(14) 563 #define CTR_L1IP_MASK U(0x3) 564 #define CTR_IMINLINE_SHIFT U(0) 565 #define CTR_IMINLINE_MASK U(0xf) 566 567 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 568 569 /* Physical timer control register bit fields shifts and masks */ 570 #define CNTP_CTL_ENABLE_SHIFT U(0) 571 #define CNTP_CTL_IMASK_SHIFT U(1) 572 #define CNTP_CTL_ISTATUS_SHIFT U(2) 573 574 #define CNTP_CTL_ENABLE_MASK U(1) 575 #define CNTP_CTL_IMASK_MASK U(1) 576 #define CNTP_CTL_ISTATUS_MASK U(1) 577 578 /* Exception Syndrome register bits and bobs */ 579 #define ESR_EC_SHIFT U(26) 580 #define ESR_EC_MASK U(0x3f) 581 #define ESR_EC_LENGTH U(6) 582 #define EC_UNKNOWN U(0x0) 583 #define EC_WFE_WFI U(0x1) 584 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 585 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 586 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 587 #define EC_AARCH32_CP14_LDC_STC U(0x6) 588 #define EC_FP_SIMD U(0x7) 589 #define EC_AARCH32_CP10_MRC U(0x8) 590 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 591 #define EC_ILLEGAL U(0xe) 592 #define EC_AARCH32_SVC U(0x11) 593 #define EC_AARCH32_HVC U(0x12) 594 #define EC_AARCH32_SMC U(0x13) 595 #define EC_AARCH64_SVC U(0x15) 596 #define EC_AARCH64_HVC U(0x16) 597 #define EC_AARCH64_SMC U(0x17) 598 #define EC_AARCH64_SYS U(0x18) 599 #define EC_IABORT_LOWER_EL U(0x20) 600 #define EC_IABORT_CUR_EL U(0x21) 601 #define EC_PC_ALIGN U(0x22) 602 #define EC_DABORT_LOWER_EL U(0x24) 603 #define EC_DABORT_CUR_EL U(0x25) 604 #define EC_SP_ALIGN U(0x26) 605 #define EC_AARCH32_FP U(0x28) 606 #define EC_AARCH64_FP U(0x2c) 607 #define EC_SERROR U(0x2f) 608 609 /* 610 * External Abort bit in Instruction and Data Aborts synchronous exception 611 * syndromes. 612 */ 613 #define ESR_ISS_EABORT_EA_BIT U(9) 614 615 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 616 617 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 618 #define RMR_RESET_REQUEST_SHIFT U(0x1) 619 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 620 621 /******************************************************************************* 622 * Definitions of register offsets, fields and macros for CPU system 623 * instructions. 624 ******************************************************************************/ 625 626 #define TLBI_ADDR_SHIFT U(12) 627 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 628 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 629 630 /******************************************************************************* 631 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 632 * system level implementation of the Generic Timer. 633 ******************************************************************************/ 634 #define CNTCTLBASE_CNTFRQ U(0x0) 635 #define CNTNSAR U(0x4) 636 #define CNTNSAR_NS_SHIFT(x) (x) 637 638 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 639 #define CNTACR_RPCT_SHIFT U(0x0) 640 #define CNTACR_RVCT_SHIFT U(0x1) 641 #define CNTACR_RFRQ_SHIFT U(0x2) 642 #define CNTACR_RVOFF_SHIFT U(0x3) 643 #define CNTACR_RWVT_SHIFT U(0x4) 644 #define CNTACR_RWPT_SHIFT U(0x5) 645 646 /******************************************************************************* 647 * Definitions of register offsets and fields in the CNTBaseN Frame of the 648 * system level implementation of the Generic Timer. 649 ******************************************************************************/ 650 /* Physical Count register. */ 651 #define CNTPCT_LO U(0x0) 652 /* Counter Frequency register. */ 653 #define CNTBASEN_CNTFRQ U(0x10) 654 /* Physical Timer CompareValue register. */ 655 #define CNTP_CVAL_LO U(0x20) 656 /* Physical Timer Control register. */ 657 #define CNTP_CTL U(0x2c) 658 659 /* PMCR_EL0 definitions */ 660 #define PMCR_EL0_RESET_VAL U(0x0) 661 #define PMCR_EL0_N_SHIFT U(11) 662 #define PMCR_EL0_N_MASK U(0x1f) 663 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 664 #define PMCR_EL0_LC_BIT (U(1) << 6) 665 #define PMCR_EL0_DP_BIT (U(1) << 5) 666 #define PMCR_EL0_X_BIT (U(1) << 4) 667 #define PMCR_EL0_D_BIT (U(1) << 3) 668 669 /******************************************************************************* 670 * Definitions for system register interface to SVE 671 ******************************************************************************/ 672 #define ZCR_EL3 S3_6_C1_C2_0 673 #define ZCR_EL2 S3_4_C1_C2_0 674 675 /* ZCR_EL3 definitions */ 676 #define ZCR_EL3_LEN_MASK U(0xf) 677 678 /* ZCR_EL2 definitions */ 679 #define ZCR_EL2_LEN_MASK U(0xf) 680 681 /******************************************************************************* 682 * Definitions of MAIR encodings for device and normal memory 683 ******************************************************************************/ 684 /* 685 * MAIR encodings for device memory attributes. 686 */ 687 #define MAIR_DEV_nGnRnE ULL(0x0) 688 #define MAIR_DEV_nGnRE ULL(0x4) 689 #define MAIR_DEV_nGRE ULL(0x8) 690 #define MAIR_DEV_GRE ULL(0xc) 691 692 /* 693 * MAIR encodings for normal memory attributes. 694 * 695 * Cache Policy 696 * WT: Write Through 697 * WB: Write Back 698 * NC: Non-Cacheable 699 * 700 * Transient Hint 701 * NTR: Non-Transient 702 * TR: Transient 703 * 704 * Allocation Policy 705 * RA: Read Allocate 706 * WA: Write Allocate 707 * RWA: Read and Write Allocate 708 * NA: No Allocation 709 */ 710 #define MAIR_NORM_WT_TR_WA ULL(0x1) 711 #define MAIR_NORM_WT_TR_RA ULL(0x2) 712 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 713 #define MAIR_NORM_NC ULL(0x4) 714 #define MAIR_NORM_WB_TR_WA ULL(0x5) 715 #define MAIR_NORM_WB_TR_RA ULL(0x6) 716 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 717 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 718 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 719 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 720 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 721 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 722 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 723 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 724 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 725 726 #define MAIR_NORM_OUTER_SHIFT U(4) 727 728 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 729 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 730 731 /* PAR_EL1 fields */ 732 #define PAR_F_SHIFT U(0) 733 #define PAR_F_MASK ULL(0x1) 734 #define PAR_ADDR_SHIFT U(12) 735 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 736 737 /******************************************************************************* 738 * Definitions for system register interface to SPE 739 ******************************************************************************/ 740 #define PMBLIMITR_EL1 S3_0_C9_C10_0 741 742 /******************************************************************************* 743 * Definitions for system register interface to MPAM 744 ******************************************************************************/ 745 #define MPAMIDR_EL1 S3_0_C10_C4_4 746 #define MPAM2_EL2 S3_4_C10_C5_0 747 #define MPAMHCR_EL2 S3_4_C10_C4_0 748 #define MPAM3_EL3 S3_6_C10_C5_0 749 750 /******************************************************************************* 751 * Definitions for system register interface to AMU for ARMv8.4 onwards 752 ******************************************************************************/ 753 #define AMCR_EL0 S3_3_C13_C2_0 754 #define AMCFGR_EL0 S3_3_C13_C2_1 755 #define AMCGCR_EL0 S3_3_C13_C2_2 756 #define AMUSERENR_EL0 S3_3_C13_C2_3 757 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 758 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 759 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 760 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 761 762 /* Activity Monitor Group 0 Event Counter Registers */ 763 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 764 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 765 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 766 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 767 768 /* Activity Monitor Group 0 Event Type Registers */ 769 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 770 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 771 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 772 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 773 774 /* Activity Monitor Group 1 Event Counter Registers */ 775 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 776 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 777 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 778 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 779 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 780 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 781 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 782 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 783 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 784 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 785 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 786 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 787 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 788 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 789 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 790 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 791 792 /* Activity Monitor Group 1 Event Type Registers */ 793 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 794 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 795 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 796 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 797 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 798 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 799 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 800 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 801 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 802 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 803 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 804 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 805 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 806 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 807 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 808 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 809 810 /* AMCGCR_EL0 definitions */ 811 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 812 #define AMCGCR_EL0_CG1NC_LENGTH U(8) 813 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 814 815 /* MPAM register definitions */ 816 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 817 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 818 819 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 820 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 821 822 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 823 824 /******************************************************************************* 825 * RAS system registers 826 ******************************************************************************/ 827 #define DISR_EL1 S3_0_C12_C1_1 828 #define DISR_A_BIT U(31) 829 830 #define ERRIDR_EL1 S3_0_C5_C3_0 831 #define ERRIDR_MASK U(0xffff) 832 833 #define ERRSELR_EL1 S3_0_C5_C3_1 834 835 /* System register access to Standard Error Record registers */ 836 #define ERXFR_EL1 S3_0_C5_C4_0 837 #define ERXCTLR_EL1 S3_0_C5_C4_1 838 #define ERXSTATUS_EL1 S3_0_C5_C4_2 839 #define ERXADDR_EL1 S3_0_C5_C4_3 840 #define ERXPFGF_EL1 S3_0_C5_C4_4 841 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 842 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 843 #define ERXMISC0_EL1 S3_0_C5_C5_0 844 #define ERXMISC1_EL1 S3_0_C5_C5_1 845 846 #define ERXCTLR_ED_BIT (U(1) << 0) 847 #define ERXCTLR_UE_BIT (U(1) << 4) 848 849 #define ERXPFGCTL_UC_BIT (U(1) << 1) 850 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 851 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 852 853 /******************************************************************************* 854 * Armv8.3 Pointer Authentication Registers 855 ******************************************************************************/ 856 #define APIAKeyLo_EL1 S3_0_C2_C1_0 857 #define APIAKeyHi_EL1 S3_0_C2_C1_1 858 #define APIBKeyLo_EL1 S3_0_C2_C1_2 859 #define APIBKeyHi_EL1 S3_0_C2_C1_3 860 #define APDAKeyLo_EL1 S3_0_C2_C2_0 861 #define APDAKeyHi_EL1 S3_0_C2_C2_1 862 #define APDBKeyLo_EL1 S3_0_C2_C2_2 863 #define APDBKeyHi_EL1 S3_0_C2_C2_3 864 #define APGAKeyLo_EL1 S3_0_C2_C3_0 865 #define APGAKeyHi_EL1 S3_0_C2_C3_1 866 867 /******************************************************************************* 868 * Armv8.4 Data Independent Timing Registers 869 ******************************************************************************/ 870 #define DIT S3_3_C4_C2_5 871 #define DIT_BIT BIT(24) 872 873 /******************************************************************************* 874 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 875 ******************************************************************************/ 876 #define SSBS S3_3_C4_C2_6 877 878 #endif /* ARCH_H */ 879