1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_config.h> 8 #include <arm_def.h> 9 #include <arm_spm_def.h> 10 #include <arm_xlat_tables.h> 11 #include <assert.h> 12 #include <cci.h> 13 #include <ccn.h> 14 #include <debug.h> 15 #include <gicv2.h> 16 #include <mmio.h> 17 #include <plat_arm.h> 18 #include <secure_partition.h> 19 #include <v2m_def.h> 20 #include "../fvp_def.h" 21 #include "fvp_private.h" 22 23 /* Defines for GIC Driver build time selection */ 24 #define FVP_GICV2 1 25 #define FVP_GICV3 2 26 #define FVP_GICV3_LEGACY 3 27 28 /******************************************************************************* 29 * arm_config holds the characteristics of the differences between the three FVP 30 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 31 * at each boot stage by the primary before enabling the MMU (to allow 32 * interconnect configuration) & used thereafter. Each BL will have its own copy 33 * to allow independent operation. 34 ******************************************************************************/ 35 arm_config_t arm_config; 36 37 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 38 DEVICE0_SIZE, \ 39 MT_DEVICE | MT_RW | MT_SECURE) 40 41 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 42 DEVICE1_SIZE, \ 43 MT_DEVICE | MT_RW | MT_SECURE) 44 45 /* 46 * Need to be mapped with write permissions in order to set a new non-volatile 47 * counter value. 48 */ 49 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 50 DEVICE2_SIZE, \ 51 MT_DEVICE | MT_RW | MT_SECURE) 52 53 54 /* 55 * Table of memory regions for various BL stages to map using the MMU. 56 * This doesn't include Trusted SRAM as arm_setup_page_tables() already 57 * takes care of mapping it. 58 * 59 * The flash needs to be mapped as writable in order to erase the FIP's Table of 60 * Contents in case of unrecoverable error (see plat_error_handler()). 61 */ 62 #ifdef IMAGE_BL1 63 const mmap_region_t plat_arm_mmap[] = { 64 ARM_MAP_SHARED_RAM, 65 V2M_MAP_FLASH0_RW, 66 V2M_MAP_IOFPGA, 67 MAP_DEVICE0, 68 MAP_DEVICE1, 69 #if TRUSTED_BOARD_BOOT 70 /* To access the Root of Trust Public Key registers. */ 71 MAP_DEVICE2, 72 /* Map DRAM to authenticate NS_BL2U image. */ 73 ARM_MAP_NS_DRAM1, 74 #endif 75 {0} 76 }; 77 #endif 78 #ifdef IMAGE_BL2 79 const mmap_region_t plat_arm_mmap[] = { 80 ARM_MAP_SHARED_RAM, 81 V2M_MAP_FLASH0_RW, 82 V2M_MAP_IOFPGA, 83 MAP_DEVICE0, 84 MAP_DEVICE1, 85 ARM_MAP_NS_DRAM1, 86 #ifdef AARCH64 87 ARM_MAP_DRAM2, 88 #endif 89 #ifdef SPD_tspd 90 ARM_MAP_TSP_SEC_MEM, 91 #endif 92 #if TRUSTED_BOARD_BOOT 93 /* To access the Root of Trust Public Key registers. */ 94 MAP_DEVICE2, 95 #endif 96 #if ENABLE_SPM 97 ARM_SP_IMAGE_MMAP, 98 #endif 99 #if ARM_BL31_IN_DRAM 100 ARM_MAP_BL31_SEC_DRAM, 101 #endif 102 #ifdef SPD_opteed 103 ARM_MAP_OPTEE_CORE_MEM, 104 ARM_OPTEE_PAGEABLE_LOAD_MEM, 105 #endif 106 {0} 107 }; 108 #endif 109 #ifdef IMAGE_BL2U 110 const mmap_region_t plat_arm_mmap[] = { 111 MAP_DEVICE0, 112 V2M_MAP_IOFPGA, 113 {0} 114 }; 115 #endif 116 #ifdef IMAGE_BL31 117 const mmap_region_t plat_arm_mmap[] = { 118 ARM_MAP_SHARED_RAM, 119 ARM_MAP_EL3_TZC_DRAM, 120 V2M_MAP_IOFPGA, 121 MAP_DEVICE0, 122 MAP_DEVICE1, 123 ARM_V2M_MAP_MEM_PROTECT, 124 #if ENABLE_SPM 125 ARM_SPM_BUF_EL3_MMAP, 126 #endif 127 {0} 128 }; 129 130 #if ENABLE_SPM && defined(IMAGE_BL31) 131 const mmap_region_t plat_arm_secure_partition_mmap[] = { 132 V2M_MAP_IOFPGA_EL0, /* for the UART */ 133 MAP_REGION_FLAT(DEVICE0_BASE, \ 134 DEVICE0_SIZE, \ 135 MT_DEVICE | MT_RO | MT_SECURE | MT_USER), 136 ARM_SP_IMAGE_MMAP, 137 ARM_SP_IMAGE_NS_BUF_MMAP, 138 ARM_SP_IMAGE_RW_MMAP, 139 ARM_SPM_BUF_EL0_MMAP, 140 {0} 141 }; 142 #endif 143 #endif 144 #ifdef IMAGE_BL32 145 const mmap_region_t plat_arm_mmap[] = { 146 #ifdef AARCH32 147 ARM_MAP_SHARED_RAM, 148 #endif 149 V2M_MAP_IOFPGA, 150 MAP_DEVICE0, 151 MAP_DEVICE1, 152 {0} 153 }; 154 #endif 155 156 ARM_CASSERT_MMAP 157 158 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 159 static const int fvp_cci400_map[] = { 160 PLAT_FVP_CCI400_CLUS0_SL_PORT, 161 PLAT_FVP_CCI400_CLUS1_SL_PORT, 162 }; 163 164 static const int fvp_cci5xx_map[] = { 165 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 166 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 167 }; 168 169 static unsigned int get_interconnect_master(void) 170 { 171 unsigned int master; 172 u_register_t mpidr; 173 174 mpidr = read_mpidr_el1(); 175 master = (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) ? 176 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 177 178 assert(master < FVP_CLUSTER_COUNT); 179 return master; 180 } 181 #endif 182 183 #if ENABLE_SPM && defined(IMAGE_BL31) 184 /* 185 * Boot information passed to a secure partition during initialisation. Linear 186 * indices in MP information will be filled at runtime. 187 */ 188 static secure_partition_mp_info_t sp_mp_info[] = { 189 [0] = {0x80000000, 0}, 190 [1] = {0x80000001, 0}, 191 [2] = {0x80000002, 0}, 192 [3] = {0x80000003, 0}, 193 [4] = {0x80000100, 0}, 194 [5] = {0x80000101, 0}, 195 [6] = {0x80000102, 0}, 196 [7] = {0x80000103, 0}, 197 }; 198 199 const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = { 200 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 201 .h.version = VERSION_1, 202 .h.size = sizeof(secure_partition_boot_info_t), 203 .h.attr = 0, 204 .sp_mem_base = ARM_SP_IMAGE_BASE, 205 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 206 .sp_image_base = ARM_SP_IMAGE_BASE, 207 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 208 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 209 .sp_ns_comm_buf_base = ARM_SP_IMAGE_NS_BUF_BASE, 210 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 211 .sp_image_size = ARM_SP_IMAGE_SIZE, 212 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 213 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 214 .sp_ns_comm_buf_size = ARM_SP_IMAGE_NS_BUF_SIZE, 215 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 216 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 217 .num_cpus = PLATFORM_CORE_COUNT, 218 .mp_info = &sp_mp_info[0], 219 }; 220 221 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 222 { 223 return plat_arm_secure_partition_mmap; 224 } 225 226 const struct secure_partition_boot_info *plat_get_secure_partition_boot_info( 227 void *cookie) 228 { 229 return &plat_arm_secure_partition_boot_info; 230 } 231 232 #endif 233 234 /******************************************************************************* 235 * A single boot loader stack is expected to work on both the Foundation FVP 236 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 237 * SYS_ID register provides a mechanism for detecting the differences between 238 * these platforms. This information is stored in a per-BL array to allow the 239 * code to take the correct path.Per BL platform configuration. 240 ******************************************************************************/ 241 void fvp_config_setup(void) 242 { 243 unsigned int rev, hbi, bld, arch, sys_id; 244 245 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 246 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 247 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 248 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 249 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 250 251 if (arch != ARCH_MODEL) { 252 ERROR("This firmware is for FVP models\n"); 253 panic(); 254 } 255 256 /* 257 * The build field in the SYS_ID tells which variant of the GIC 258 * memory is implemented by the model. 259 */ 260 switch (bld) { 261 case BLD_GIC_VE_MMAP: 262 ERROR("Legacy Versatile Express memory map for GIC peripheral" 263 " is not supported\n"); 264 panic(); 265 break; 266 case BLD_GIC_A53A57_MMAP: 267 break; 268 default: 269 ERROR("Unsupported board build %x\n", bld); 270 panic(); 271 } 272 273 /* 274 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 275 * for the Foundation FVP. 276 */ 277 switch (hbi) { 278 case HBI_FOUNDATION_FVP: 279 arm_config.flags = 0; 280 281 /* 282 * Check for supported revisions of Foundation FVP 283 * Allow future revisions to run but emit warning diagnostic 284 */ 285 switch (rev) { 286 case REV_FOUNDATION_FVP_V2_0: 287 case REV_FOUNDATION_FVP_V2_1: 288 case REV_FOUNDATION_FVP_v9_1: 289 case REV_FOUNDATION_FVP_v9_6: 290 break; 291 default: 292 WARN("Unrecognized Foundation FVP revision %x\n", rev); 293 break; 294 } 295 break; 296 case HBI_BASE_FVP: 297 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 298 299 /* 300 * Check for supported revisions 301 * Allow future revisions to run but emit warning diagnostic 302 */ 303 switch (rev) { 304 case REV_BASE_FVP_V0: 305 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 306 break; 307 case REV_BASE_FVP_REVC: 308 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 309 ARM_CONFIG_FVP_HAS_CCI5XX); 310 break; 311 default: 312 WARN("Unrecognized Base FVP revision %x\n", rev); 313 break; 314 } 315 break; 316 default: 317 ERROR("Unsupported board HBI number 0x%x\n", hbi); 318 panic(); 319 } 320 321 /* 322 * We assume that the presence of MT bit, and therefore shifted 323 * affinities, is uniform across the platform: either all CPUs, or no 324 * CPUs implement it. 325 */ 326 if (read_mpidr_el1() & MPIDR_MT_MASK) 327 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 328 } 329 330 331 void fvp_interconnect_init(void) 332 { 333 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 334 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 335 ERROR("Unrecognized CCN variant detected. Only CCN-502" 336 " is supported"); 337 panic(); 338 } 339 340 plat_arm_interconnect_init(); 341 #else 342 uintptr_t cci_base = 0; 343 const int *cci_map = 0; 344 unsigned int map_size = 0; 345 346 if (!(arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 347 ARM_CONFIG_FVP_HAS_CCI5XX))) { 348 return; 349 } 350 351 /* Initialize the right interconnect */ 352 if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) { 353 cci_base = PLAT_FVP_CCI5XX_BASE; 354 cci_map = fvp_cci5xx_map; 355 map_size = ARRAY_SIZE(fvp_cci5xx_map); 356 } else if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) { 357 cci_base = PLAT_FVP_CCI400_BASE; 358 cci_map = fvp_cci400_map; 359 map_size = ARRAY_SIZE(fvp_cci400_map); 360 } 361 362 assert(cci_base); 363 assert(cci_map); 364 cci_init(cci_base, cci_map, map_size); 365 #endif 366 } 367 368 void fvp_interconnect_enable(void) 369 { 370 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 371 plat_arm_interconnect_enter_coherency(); 372 #else 373 unsigned int master; 374 375 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 376 ARM_CONFIG_FVP_HAS_CCI5XX)) { 377 master = get_interconnect_master(); 378 cci_enable_snoop_dvm_reqs(master); 379 } 380 #endif 381 } 382 383 void fvp_interconnect_disable(void) 384 { 385 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 386 plat_arm_interconnect_exit_coherency(); 387 #else 388 unsigned int master; 389 390 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 391 ARM_CONFIG_FVP_HAS_CCI5XX)) { 392 master = get_interconnect_master(); 393 cci_disable_snoop_dvm_reqs(master); 394 } 395 #endif 396 } 397