1# 2# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture major and minor versions: 8.0 by default. 23ARM_ARCH_MAJOR := 8 24ARM_ARCH_MINOR := 0 25 26# Determine the version of ARM GIC architecture to use for interrupt management 27# in EL3. The platform port can change this value if needed. 28ARM_GIC_ARCH := 2 29 30# Base commit to perform code check on 31BASE_COMMIT := origin/master 32 33# Execute BL2 at EL3 34BL2_AT_EL3 := 0 35 36# BL2 image is stored in XIP memory, for now, this option is only supported 37# when BL2_AT_EL3 is 1. 38BL2_IN_XIP_MEM := 0 39 40# By default, consider that the platform may release several CPUs out of reset. 41# The platform Makefile is free to override this value. 42COLD_BOOT_SINGLE_CPU := 0 43 44# Flag to compile in coreboot support code. Exclude by default. The coreboot 45# Makefile system will set this when compiling TF as part of a coreboot image. 46COREBOOT := 0 47 48# For Chain of Trust 49CREATE_KEYS := 1 50 51# Build flag to include AArch32 registers in cpu context save and restore during 52# world switch. This flag must be set to 0 for AArch64-only platforms. 53CTX_INCLUDE_AARCH32_REGS := 1 54 55# Include FP registers in cpu context 56CTX_INCLUDE_FPREGS := 0 57 58# Debug build 59DEBUG := 0 60 61# Build platform 62DEFAULT_PLAT := fvp 63 64# Enable capability to disable authentication dynamically. Only meant for 65# development platforms. 66DYN_DISABLE_AUTH := 0 67 68# Build option to enable MPAM for lower ELs 69ENABLE_MPAM_FOR_LOWER_ELS := 0 70 71# Flag to enable Performance Measurement Framework 72ENABLE_PMF := 0 73 74# Flag to enable PSCI STATs functionality 75ENABLE_PSCI_STAT := 0 76 77# Flag to enable runtime instrumentation using PMF 78ENABLE_RUNTIME_INSTRUMENTATION := 0 79 80# Flag to enable stack corruption protection 81ENABLE_STACK_PROTECTOR := 0 82 83# Flag to enable exception handling in EL3 84EL3_EXCEPTION_HANDLING := 0 85 86# Build flag to treat usage of deprecated platform and framework APIs as error. 87ERROR_DEPRECATED := 0 88 89# Fault injection support 90FAULT_INJECTION_SUPPORT := 0 91 92# Byte alignment that each component in FIP is aligned to 93FIP_ALIGN := 0 94 95# Default FIP file name 96FIP_NAME := fip.bin 97 98# Default FWU_FIP file name 99FWU_FIP_NAME := fwu_fip.bin 100 101# For Chain of Trust 102GENERATE_COT := 0 103 104# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 105# default, they are for Secure EL1. 106GICV2_G0_FOR_EL3 := 0 107 108# Route External Aborts to EL3. Disabled by default; External Aborts are handled 109# by lower ELs. 110HANDLE_EA_EL3_FIRST := 0 111 112# Whether system coherency is managed in hardware, without explicit software 113# operations. 114HW_ASSISTED_COHERENCY := 0 115 116# Set the default algorithm for the generation of Trusted Board Boot keys 117KEY_ALG := rsa 118 119# Enable use of the console API allowing multiple consoles to be registered 120# at the same time. 121MULTI_CONSOLE_API := 0 122 123# NS timer register save and restore 124NS_TIMER_SWITCH := 0 125 126# Build PL011 UART driver in minimal generic UART mode 127PL011_GENERIC_UART := 0 128 129# By default, consider that the platform's reset address is not programmable. 130# The platform Makefile is free to override this value. 131PROGRAMMABLE_RESET_ADDRESS := 0 132 133# Flag used to choose the power state format viz Extended State-ID or the 134# Original format. 135PSCI_EXTENDED_STATE_ID := 0 136 137# Enable RAS support 138RAS_EXTENSION := 0 139 140# By default, BL1 acts as the reset handler, not BL31 141RESET_TO_BL31 := 0 142 143# For Chain of Trust 144SAVE_KEYS := 0 145 146# Software Delegated Exception support 147SDEI_SUPPORT := 0 148 149# Whether code and read-only data should be put on separate memory pages. The 150# platform Makefile is free to override this value. 151SEPARATE_CODE_AND_RODATA := 0 152 153# Default to SMCCC Version 1.X 154SMCCC_MAJOR_VERSION := 1 155 156# SPD choice 157SPD := none 158 159# For including the Secure Partition Manager 160ENABLE_SPM := 0 161 162# Flag to introduce an infinite loop in BL1 just before it exits into the next 163# image. This is meant to help debugging the post-BL2 phase. 164SPIN_ON_BL1_EXIT := 0 165 166# Flags to build TF with Trusted Boot support 167TRUSTED_BOARD_BOOT := 0 168 169# Build option to choose whether Trusted firmware uses Coherent memory or not. 170USE_COHERENT_MEM := 1 171 172# Build option to choose wheter Trusted firmware uses library at ROM 173USE_ROMLIB := 0 174 175# Use tbbr_oid.h instead of platform_oid.h 176USE_TBBR_DEFS = $(ERROR_DEPRECATED) 177 178# Build verbosity 179V := 0 180 181# Whether to enable D-Cache early during warm boot. This is usually 182# applicable for platforms wherein interconnect programming is not 183# required to enable cache coherency after warm reset (eg: single cluster 184# platforms). 185WARMBOOT_ENABLE_DCACHE_EARLY := 0 186 187# Build option to enable/disable the Statistical Profiling Extensions 188ENABLE_SPE_FOR_LOWER_ELS := 1 189 190# SPE is only supported on AArch64 so disable it on AArch32. 191ifeq (${ARCH},aarch32) 192 override ENABLE_SPE_FOR_LOWER_ELS := 0 193endif 194 195ENABLE_AMU := 0 196 197# By default, enable Scalable Vector Extension if implemented for Non-secure 198# lower ELs 199# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 200ifneq (${ARCH},aarch32) 201 ENABLE_SVE_FOR_NS := 1 202else 203 override ENABLE_SVE_FOR_NS := 0 204endif 205